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Design of a Messageflow Processor with Chip-based Inter-processors Communication Function

Research Project

Project/Area Number 09558031
Research Category

Grant-in-Aid for Scientific Research (B)

Allocation TypeSingle-year Grants
Section展開研究
Research Field 計算機科学
Research InstitutionKYOTO INSTITUTE OF TECHNOLOGY

Principal Investigator

SHIBAYAMA Kiyoshi  Eng. & Design, Kyoto Inst. Tech., Prof., 工芸学部, 教授 (70127091)

Co-Investigator(Kenkyū-buntansha) NAKATA Toshiyuki  C&C Media Research Inst., NEC, Head Researcher, C&Cメディア研究所, 研究部長
NIIMI Haruo  Eng., Kyoto Sangyo Univ., Prof., 工学部, 教授 (40144331)
HIRATA Hiroaki  Eng. & Design, Kyoto Inst. Tech., Associate Prof., 工芸学部, 助教授 (90273549)
北村 俊明  富士通(株), グローバルサーバ部, 課長(研究職)
Project Period (FY) 1997 – 1999
Project Status Completed (Fiscal Year 1999)
Budget Amount *help
¥11,400,000 (Direct Cost: ¥11,400,000)
Fiscal Year 1999: ¥4,900,000 (Direct Cost: ¥4,900,000)
Fiscal Year 1998: ¥3,400,000 (Direct Cost: ¥3,400,000)
Fiscal Year 1997: ¥3,100,000 (Direct Cost: ¥3,100,000)
KeywordsMessageflow / Onchip / Inter-processors Communication / Computer Architecture / Thread / Computation Model
Research Abstract

"Active Messages (AM) " has been proposed as an efficient message passing communication scheme for distributed memory parallel computers. AM is one of the best message passing communication schemes, and therefore AM has been implemented on several parallel computers to achieve the dramatic performance improvements. The novel feature of AM is that, in an inter-processor communication message, it is specified how the receiving processor should handle the message.
In this research, we present a new communication scheme which improves AM in both the performance and availability. We call our scheme "Active Threaded Message (AT-Message) ". AT-Message is implemented by using two threads, which are independent control flows executed on each processor. One thread is for calculation, and the other for handling of received messages. These two threads are executed in parallel to achieve the low overhead communication. Furthermore, on designing AT-Message, we had investigated the optimal trade-off point between the software (such as a user program and an OS) and the hardware (such as a processor and a network controller), and we could succeed to realize both of safety and high-performance in the user-level communication of AT-Message. By employing AT-Message, we can construct an higher-performance and more easily-programmable massively parallel computer than the case employing original AM.
In this research, we also present a detailed design of the elementary processor architecture implementing AT-Message efficiently.

Report

(4 results)
  • 1999 Annual Research Report   Final Research Report Summary
  • 1998 Annual Research Report
  • 1997 Annual Research Report
  • Research Products

    (25 results)

All Other

All Publications (25 results)

  • [Publications] 平田博章: "マルチスレッドプロセッサおよび1チップマルチプロセッサのための命令キャッシュ構成・命令フェッチ方式の性能評価"電子情報通信学会・論文誌. J81-D-I,5. 718-727 (1998)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] 布目淳: "時間的負荷変化量を考慮した超並列計算機向き動的負荷分散方式"電子情報通信学会・技術研究報告. CPSY-98-70. 73-80 (1998)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] 本河俊樹: "再帰的データ構造を対象としたループの並列投機実行方式"情報処理学会・研究報告. ARC-136-1. 1-6 (2000)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] 天津克秀: "分散メモリ型並列計算機向きスレッドスケジューリング方式"電子情報通信学会・論文誌. J80-D-I,7. 615-623 (1997)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] 野中恵三: "並列処理による重力多体問題の解法の高速化"情報処理学会・研究報告(HOKKE-97論文集). HPC-65-8. 39-44 (1997)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] 柴山潔: "コンピュータアーキテクチャ"オーム社. 413 (1997)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Hiroaki HIRATA: "Performance Comparisons of Instruction Cache Configurations and Instruction Fetch Schemes for a Multithreaded Processor or a 1-Chip Multiprocessor"Trans. IEICE. J81-D-I-5. 718-727 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Atsushi NUNOME: "Dynamically Load Balancing Scheme Considering the Load Variation Speed for Massively Parallel Computers"IEICE Technical Report. CPSY-98-70. 73-80 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Toshiki MOTOKAWA: "Parallel Execution of Loop Iterations by Speculative Traversal on Recursive Data Structures"IPSJ SIG Notes. ARC-136-1. 1-6 (2000)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Katsuhide AMATSU: "Studies of Hierarchical Thread Scheduling for Distributed Memory Parallel Processors"Trans. IEICE. J80-D-I-7. 615-623 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Keizo NONAKA: "To Speed-up Gravitational N-body Problem Solving by Parallel Processing"IPSJ-SIG Notes. HPC-65-8. 39-44 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] Kiyoshi SHIBAYAMA: "Coputer Architecture"OHM-sha. 413 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      1999 Final Research Report Summary
  • [Publications] 平田 博章: "マルチスレッドプロセッサおよび1チップマルチプロセッサのための命令キャッシュ構成・命令フェッチ方式の性能評価"電子情報通信学会・論文誌. J81-D-I,5. 718-727 (1998)

    • Related Report
      1999 Annual Research Report
  • [Publications] 布目 淳: "時間的負荷変化量を考慮した超並列計算機向き動的負荷分散方式"電子情報通信学会・技術研究報告. CPSY-98-70. 73-80 (1998)

    • Related Report
      1999 Annual Research Report
  • [Publications] 本河 俊樹: "再帰的データ構造を対象としたループの並列投機実行方式"情報処理学会・研究報告. ARC-136-1. 1-6 (2000)

    • Related Report
      1999 Annual Research Report
  • [Publications] 天津 克秀: "分散メモリ型並列計算機向きスレッドスケジューリング方式"電子情報通信学会・論文誌. J80-D-1,7. 615-623 (1997)

    • Related Report
      1999 Annual Research Report
  • [Publications] 野中 恵三: "並列処理による重力多体問題の解法の高速化"情報処理学会・研究報告(HOKKE-97論文集). HPC-65-8. 39-44 (1997)

    • Related Report
      1999 Annual Research Report
  • [Publications] 柴山 潔: "コンピュータアーキテクチャ"オーム社. 413 (1997)

    • Related Report
      1999 Annual Research Report
  • [Publications] 平田 博章: "マルチスレッドプロセッサおよび1チップマルチプロセッサのための命令キャッシュ構成・命令フェッチ方式の性能評価" 電子情報通信学会・論文誌. J81-D-I-5. 718-727 (1998)

    • Related Report
      1998 Annual Research Report
  • [Publications] 布目 淳: "時間的負荷変化量を考慮した超並列計算機向き動的負荷分散方式" 電子情報通信学会・技術研究報告. CPSY98-70. 73-80 (1998)

    • Related Report
      1998 Annual Research Report
  • [Publications] 勝部 耕太郎: "数値属性間最適結合ルール生成の並列処理方式" Parallel Computing Workshop '98 Japan. P-J. 1-4 (1998)

    • Related Report
      1998 Annual Research Report
  • [Publications] 野中 恵三: "並列処理による重力多体問題の解法の高速化" 情報処理学会・研究報告. 97-HPC-65. 39-44 (1997)

    • Related Report
      1997 Annual Research Report
  • [Publications] 天津 克秀: "分散メモリ型並列計算機向き階層化スレッドスケジューリング方式" 電子情報通信学会・論文誌. J80-D-I-7. 615-623 (1997)

    • Related Report
      1997 Annual Research Report
  • [Publications] 平田 博章: "マルチスレッドプロセッサおよび1チップマルチプロセッサのための命令キャッシュ構成・命令フェッチ方式の性能評価" 電子情報通信学会・論文誌. J81-D-I-5(掲載予定). (1998)

    • Related Report
      1997 Annual Research Report
  • [Publications] 柴山 潔: "ハードウェア入門" サイエンス社, 153 (1997)

    • Related Report
      1997 Annual Research Report

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Published: 1997-04-01   Modified: 2016-04-21  

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