RESEARCH OF HOUGH TRANSFORM HARDWARE EMPLOYING QUADRUPLE RECURRENCE FORMULA
Project/Area Number  09650498 
Research Category 
GrantinAid for Scientific Research (C)

Allocation Type  Singleyear Grants 
Section  一般 
Research Field 
計測・制御工学

Research Institution  KURUME NATIONAL COLLEGE OF TECHNOLOGY 
Principal Investigator 
NAKASHIMA Katsuyuki KURUME NATIONAL COLLEGE OF TECHNOLOGY, ELECTRIC ENGINEERlNG DEPARTMENT, ASSISTANT PROFESSOR, 電気工学科, 助教授 (00124131)

CoInvestigator(Kenkyūbuntansha) 
INOUE Katsunori JOINT AND WELDING RESEARCH INSTITUTE OF OSAKA UNIVERSITY, PROFESSOR, 接合科学研究所・加工システム研究部門, 教授 (90029067)
OBUCHI Yutaka KURUME NATIONAL COLLEGE OF TECHNOLOGY, ELECTRIC ENGINEERING DEPARTMENT, PROFESSO, 電気工学科, 教授 (60141959)

Project Period (FY) 
1997 – 1998

Project Status 
Completed(Fiscal Year 1998)

Budget Amount *help 
¥2,100,000 (Direct Cost : ¥2,100,000)
Fiscal Year 1998 : ¥900,000 (Direct Cost : ¥900,000)
Fiscal Year 1997 : ¥1,200,000 (Direct Cost : ¥1,200,000)

Keywords  Hough Transform / algorithm / quadruple recurrence formula / FPGA / High Speed Hough Transform Hardware / アルゴリスム / 高速ハフ変換ハードウェア / 高速ハフ変換 / 連立漸化式 / 専用ハードウエア / キャリー伝搬速度 / パイプライン方式 / 高速加算器 / メモリアクセス速度 / 高速SRAM 
Research Abstract 
On the basic research we had beforehand, the Hough transform algorithm employing new concept which includes quadruple recurrence formula was inspected again from another point of view. 'This new algorithm includes an assumption which the calculation of sinusoidal function value for given small change of angle (DELTA) is replaced by DELTA, so a small amount of error is anticipated. In the presumption of error for true value using computer simulation, we employed the floating point variables, but it is found that the hardware logic circuit designing become a little bit difficult and the amount of circuit become to have large complexity if using floating point variables. And there was more important problem that the throughput of the circuit decrease greatly. So we examined that the floating point variables are replaced by the fixed decimal point variables with minor and sign bit. The error will be decreased when the number of minor digit become large. In this case the calculation error is
… More
influenced by number of minor part binary digit. As the result of try and error examination on computer simulation, we got how to decide the minor part bit length, that is to decide the bit length as long as the error caused by shortening the minor part bit length is sufficiently ignored comparing the error caused by assumption described above. Finally the total bit length of variables were decided 20 bit with 11 bit for integer part include sign bit and 9 bit for minor part. In this case, number of division of theta axis is 402[dot], maximum value of rho is 568 [dot]. The maximum error is generated at angle theta=pi/4 and it is 1.7 [dot], On the base of this data, we designed the actual logic circuitry. We decided the main part of logic circuit is consist of FPGA (Field Programmable Gate Array), and employing special circuit emulator the validity of algorithm with fixed point variables was examined. As the result the transformation time for one point on the XY plane was turned out generally and logic design was decided on. The next stage was programing of logic circuit into FPGA.Corresponding quadruple recurrence formula for Hough transform, The logic circuit generates 4 rho Value at a same time. So we used 4 middle size SRAM (Static Random Access Memory) which accumulate the time of passing frequency of Hough curve. This makes the hardware logic circuit debugging time shorten and is very suitable for utilizing distributed parallel computer system like "Transputer". The experimental device worked completely because of our careful pre work. It was cleared that the total transform time for one point on thetarho plane depend upon the memory cycle time which accumulate the passing frequency of hough curve rather than rho value generating time. At last, eliminating the low speed FPGAS, we obtained the rho value generating time ; 80 [nsJ, accumulating time on thetarho plane ; 100 [ns]. Then the latter become the bottleneck of processing speed, we finally got lOOtnsI as the total system operating time for one point of thetarho plane. Less

Report
(3results)
Research Output
(7results)