Research on Multithreaded Massively Parallel Computers
Grant-in-Aid for Scientific Research (C)
|Research Institution||The University of Tokyo|
SAKAI Shuichi The University of Tokyo, Department of Electrical Engineering, Associate Professor, 大学院・工学系研究科電気工学専攻, 助教授 (50291290)
|Project Fiscal Year
1997 – 1998
Completed(Fiscal Year 1998)
|Budget Amount *help
¥3,200,000 (Direct Cost : ¥3,200,000)
Fiscal Year 1998 : ¥1,400,000 (Direct Cost : ¥1,400,000)
Fiscal Year 1997 : ¥1,800,000 (Direct Cost : ¥1,800,000)
|Keywords||multithreading / VLSI / Massiverly Parallel Architecuture / pipelining / synchronization mechanisms / integration of computation and communication / inter-processor communication / evaluations by simulation / マルチスレッディング / 超並列アーキテクチャ / パイプライニング / 同期機構 / 通信と計算の融合 / プロセッサ間通信 / シミュレーション評価|
The research results of this projects are listed below.
1. Performance evaluations of multithreaded massively parallel computers
Performance of multithreaded massively parallel computers were evaluated by using a parallel computer EM-4 and a massively parallel computer RWC-1. Parallel primitives such as synchronization mechanisms, pipeline structure, message handling mechanisms were evaluated and the whole system performance was examined. Examples of benchmarks were (1) radix sort, (2) sparse matrix calculations and (3) dense matrix calculations such as Linpack. The evaluation results showed that the proposed multithreaded architecture is fairly effective for the wide variety of applications.
2. Proposal and performance evaluations of I/O systems for multithreaded parallel computers
The I/O systems for multithreaded massively parallel computers were proposed and evaluted by using a real system. The evaluation showed that we can construct efficient parallel I/O system under the model of mul
3. Proposal and early evaluations of a new processor architecture
As a new processor architecture exploiting device technologies in 21st century, we proposed both an on-chip multiprocessor architecture and an architecture integrating a processor and memories. Especially for the high-performance computing, we examined the architecture where a single LSI contains a processor and a high-speed memory and the large storage is implemented outside of it. By using the internal memory as a temporal storage, this architecture can hide memory latency. It can also provide data fairly quickly if they are reused in the LSI.
The fundamental part of the processor based on the architecture was designed on the base of MIPS R10000 architecture, and a simulator was constructed. We made early evaluations using benchmarks such as Liver-more Kernel and Linpack. The evaluation results showed that the nearly ideal performance was obtained, and we can say that the part of basic technologies for the future HPC (sustainted performance 100 TFLOPS) was established.
4. Proposal and evaluations of interconnection networks for massively parallel computers
We examined the architecture of interconnection networks for massively parallel computers, and proposed the buffer control method which can drastically increase communication throughput.
The results described above have been presented in English journals, Japanese journals and conferences, and have got a lot of favorable criticisms. Less
Research Output (24results)