Investigation of high performance three-dimensional integrated circuits using three dimensional MOS devices
Grant-in-Aid for Scientific Research (B)
|Allocation Type||Single-year Grants|
|Research Institution||TOHOKU UNIVERSITY|
ENDOH Tetsuo Research Institute of Electrical Communication, Tohoku University, Assistant Professor, 電気通信研究所, 助教授 (00271990)
SAKURABA Hiroshi Research Institute of Electrical Communication, Tohoku University, Research Associate, 電気通信研究所, 助手 (60241527)
MASUOKA Fujio Research Institute of Electrical Communication, Tohoku University, Professor, 電気通信研究所, 教授 (50270822)
|Project Period (FY)
1998 – 1999
Completed(Fiscal Year 1999)
|Budget Amount *help
¥12,700,000 (Direct Cost : ¥12,700,000)
Fiscal Year 1999 : ¥5,800,000 (Direct Cost : ¥5,800,000)
Fiscal Year 1998 : ¥6,900,000 (Direct Cost : ¥6,900,000)
|Keywords||MOS transistor / Three dimensional MOS transistor / SGT / Three dimensional integrated circuit / 3次元MOSFET|
(1) Design and fabrication of SGT-type three-dimensional MOS transistor and its basic circuits.
The design system for the elementary three-dimensional transistor and three dimensional circuit were set-up and calibrated. The process flow to make the designed SGT type three dimensional MOS transistor and the elementary three-dimensional circuits were established.
(2) Clarifying the specific design parameters for the three-dimensional integrated circuit.
Evaluation system for three dimensional integrated circuit was constructed. By using this system, the SGT type three-dimensional MOS transistor and the elemental three dimensional circuit were evaluated. As a result of this evaluation, the specific design parameters for three-dimensional circuit was clarified.
(3) Proposal of a high packing density three dimensional memory
The Stacked Surrounding Gate Transistor (S-SGT)DRAM is proposed as a high packing density three-dimensional memory structure, according to the design rule for proposed three dimensional integrated circuit. This memory was structured by stacking several SGT-type cells in series vertically. S-SGT DRAM was realized by new three-dimensional stacking memory array technologies. It was clarified that the S-SGT DRAM which had the 4 stacking cells can achieve the cell size of 1.44FィイD12ィエD1 where the conventional DRAM can realize the 12FィイD12ィエD1.
(4) Design investigation of a high packing density three dimensional memory
S-SGT DRAM process design was proposed and a cell size of 2.4FィイD12ィエD1 was realized.
In summary, the above given investigations resulted in a systematic, clarification of the basic design rule of SGT and of the corresponding three-dimensional integrated circuit architecture.
Research Output (5results)