| Project/Area Number | 10650334 |
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
電子デバイス・機器工学
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| Research Institution | Nagoya Institute of Technology |
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Principal Investigator |
ARAI Eisuke Faculty of Engineering, Electrical and Computer Engineering, Prof., 工学部・電気情報工学科, 教授 (90283473)
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| Co-Investigator(Kenkyū-buntansha) |
UCHIDA Hideo Faculty of Engineering, Electrical and Computer Engineering, Nagoya Institute of Technology Res.Associate, 工学部, 助手 (10293739)
SHAO Chunlin Research Center for Micro-Structure Devices, Nagoya Institute of Technology Associate Prof., 極微構造デバイス研究センター, 助教授 (20242828)
ICHIMURA Masaya Faculty of Engineering, Electrical and Computer Engineering, Nagoya Institute of Technology Associate Prof., 工学部, 助教授 (30203110)
YOSHIDA Masayuki Yoshida Semiconductor Lab., Head, 所長 (80038984)
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| Project Period (FY) |
1998 – 2000
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| Project Status |
Completed(Fiscal Year 2000)
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| Budget Amount *help |
¥3,700,000 (Direct Cost : ¥3,700,000)
Fiscal Year 2000 : ¥800,000 (Direct Cost : ¥800,000)
Fiscal Year 1999 : ¥1,300,000 (Direct Cost : ¥1,300,000)
Fiscal Year 1998 : ¥1,600,000 (Direct Cost : ¥1,600,000)
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| Keywords | silicon LSI / ultra thin SOI / buried oxide / active layer / carrier concentration / spreading resistance / impurity diffusion / process simulation / プロセスシミュレータ / シリコン / SOI / シュミレーションモデル / 格子間Si / LSI / 低消費電力LSI / シミュレーションモデル / 埋込酸化膜 |
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| Research Abstract |
To develop the ultra thin SOI substrates which is expected as ones for future LSIs with higher speed and lower power performance, we studied (i) the accurate measurement method of carrier concentration profiles in SOIs, and (ii) estimation of crystalline quality of SOIs, and extraction of modeling parameters of impurity diffusion in SOIs for process simulation. Results obtained are as follows :
(1) Carrier concentration profiles in SOIs were measured by spreading resistance method. For as-received p-and n-type SOI samples, there is a carrier-depleted (highly resistive ) layer near the interface of SOI and buried oxide. For samples annealed at high temperatures near 1000℃, the carrier-depleted layer changes to inversion layer for p-type SOIs and to accumulation layer for n-type SOIs. The changes with annealing can be explained by assuming the positive charge in buried oxide and the decrease of interface state density.
(2) Phosphorus and boron diffusion profiles in ultra thin SOIs involving SIMOX, UNIBOND and Eltran were compared with those in bulk substrates. The diffusion in such SOIs is retarded, compared with that in bulk substrates. Among ultra thin SOIs the diffusion in SIMOX is most retarded, compared with that in other SOIs. The diffusion retardation rate is considered to reflect the crystalline quality of buried oxide interface and SOI substrate. Furthermore, diffusion modeling parameters for process simulation were extracted from the measured profiles in SOI.
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