|Budget Amount *help
¥3,300,000 (Direct Cost: ¥3,300,000)
Fiscal Year 1999: ¥1,300,000 (Direct Cost: ¥1,300,000)
Fiscal Year 1998: ¥2,000,000 (Direct Cost: ¥2,000,000)
The aim of this research is to develop a genetic algorithm (GA), which is able to adjust the values of genetic parameters during the algorithm execution, and is suitable for hardware implementation.
In 1998, we developed a GA hardware called GAA-II, which selected the crossover operators and mutation rates based on the superiority of an individual. GAA-II can be used as a stand-alone core processor of a hardware GA system. It can also be used to implement a parallel GA by connecting a set of GAA-II chips. GAA-II was designed with the Verilog hardware description language, and implemented as an LSI chip in the chip fabrication program of VLSI Design and Education Center (VDEC), the University of Tokyo. Compared with the ordinary software GA, GAA-II runs 20 to 50 times faster than that to get the same results.
In 1999, we developed an evaluation board to evaluate the GAA-II chip. From the experiments with the evaluation board, it was confirmed that the basic functions of the GAA-II chip were correctly implemented. As an extension of GAA-II, we also investigated a parallel GA, which had a function of adaptive parameter adjustment, and was based on a hierarchical population model. In this parallel GA, GA parameters were exchanged among subpopulations during the GA execution to obtain good results in a short computation time. Experimental results showed the effectiveness of the proposed adaptive parallel GA.
Results obtained in this research were presented in several international and domestic conferences and workshops, and published as journal papers. From this research, many fruitful results have been obtained, which will be useful for future research on genetic algorithms and their hardware implementation.