| Project/Area Number |
12044209
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| Research Category |
Grant-in-Aid for Scientific Research on Priority Areas
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| Allocation Type | Single-year Grants |
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| Review Section |
Science and Engineering
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| Research Institution | Osaka University |
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Principal Investigator |
SHIRAKAWA Isao Osaka University, Graduate School of Information Science and Technology, Professor, 大学院・情報科学研究科, 教授 (10029100)
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| Co-Investigator(Kenkyū-buntansha) |
ONOYE Takao Osaka University, Graduate School of Information Science and Technology, Professor, 大学院・情報科学研究科, 教授 (60252590)
TAKEUCHI Yoshinori Osaka University, Graduate School of Information Science and Technology, Associate Professor, 大学院・情報科学研究科, 助教授 (70242245)
安浦 寛人 九州大学, 大学院・システム情報科学研究科, 教授 (80135540)
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| Project Period (FY) |
2000 – 2002
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| Project Status |
Completed (Fiscal Year 2003)
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| Budget Amount *help |
¥123,000,000 (Direct Cost: ¥123,000,000)
Fiscal Year 2002: ¥31,700,000 (Direct Cost: ¥31,700,000)
Fiscal Year 2001: ¥31,300,000 (Direct Cost: ¥31,300,000)
Fiscal Year 2000: ¥60,000,000 (Direct Cost: ¥60,000,000)
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| Keywords | Image Coding / VLSI / JPEG2000 / Processor / IP-base Design / メディア処理 / プロセッサシステム / VLSIアーキテクチャ / システムオンチップ設計 / 低消費電力 / 組込み機器 |
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| Research Abstract |
A novel design famework is proposed for exploring JPEG2000 encoder architecture. Through the use of this framework, a designer can implement various types of JPEG2000 encoders referring to its specification, i.e. image resolution, performance requirements, power consumption, fabrication technology, chip size limitation. In order to utilize the scalablility of JPEG2000 algorithm aggressively, each procedure of JPEG2000 encoding is selectively implemented in this framework among those by software, software accelerated with user-defined instructions, or dedicated hardware. To embody such a Plug-and-Play like feature, each hardware module is designed to have a generic SRAM-based interface which can support various bus architectures by only designing interface converters. Therefore, our framework makes it much easier to design a JPEG2000 encoding system than conventional tedious manual design tasks of each procedure, which would be implemented as software or hardware. Dedicated hardware modules as well as software acceleration are devised to be used in the framework, and an LSI is fabricated to exemplify the system implementation designed through the use of our framework.
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