Design of a Super-ffigh'-Speed RSA Encryption Processor Based on the Residue Table for Redundant Binary Numbers
| Project/Area Number |
12650453
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Control engineering
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| Research Institution | Hacbinohe Institute of Technology |
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Principal Investigator |
TOMABECHI Nobuhiro Hacbinohe Institute of Technology, Faculty of Engineering, Professor, 工学部, 教授 (70048180)
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| Project Period (FY) |
2000 – 2001
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| Project Status |
Completed (Fiscal Year 2001)
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| Budget Amount *help |
¥1,800,000 (Direct Cost: ¥1,800,000)
Fiscal Year 2001: ¥700,000 (Direct Cost: ¥700,000)
Fiscal Year 2000: ¥1,100,000 (Direct Cost: ¥1,100,000)
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| Keywords | RSA cryptsystem / high-speed / Dprocessor / redundant binary number / residue table / design |
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| Research Abstract |
(1) Detailed Design of the Encryption Processor
The RSA encryption processor with following features is designed.
【encircled 1】All the arithmetic operations are performed in the form of the redundant binary arithmetic.
【encircled 2】Residue calculation is performed by table-look-up where the table is built in the hardware of the processor.
Following results are obtained.
【encircled 1】The operation speed is about 3 Mbits/sec when the key length, N is 1024 bits.
【encircled 2】The speed is almost 60 times that of the conventional processors. ^
【encircled 3】The order of the operation speed is O(NlogN). The order of the conventional processors is O(N^2).
【encircled 4】The chip size is (4.3 x 10^5λ)x(5,63 x 10^5λ), where λ denotes the standard size in the layout design.
(2) Defect-Tolerance Design of the Processor
The following method is presented.
【encircled 1】The targeted system is designed in the bit-slice form, and a bit-slice is taken as the unit block for redundancy.
【encircled 2】Redundant blocks are uniformly distributed among the non-redundant blocks.
【encircled 3】The function of me defective block is stopped and is sifted to the neighboring block.
(3) Pipelined Design of the Processor
All the partial products in the multiplier circuit are totaled using the combination of the binary tree structure with the array structure of the redundant binary adders. By the introduction pf the pipelining, fee encryption speed is greatly enhanced when the plaintext data is continuously input and the timing design becomes easy.
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Report
(3 results)
Research Products
(13 results)
