| Budget Amount *help |
¥3,700,000 (Direct Cost: ¥3,700,000)
Fiscal Year 2002: ¥500,000 (Direct Cost: ¥500,000)
Fiscal Year 2001: ¥2,400,000 (Direct Cost: ¥2,400,000)
Fiscal Year 2000: ¥800,000 (Direct Cost: ¥800,000)
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| Research Abstract |
Low-power circuit design while maintaining a high-speed capability is needed not only for battery-powered portable applications but also to reduce the power dissipation of dedicated apecial-purpose VLSI processors, because the extra current density in interconnections causes temporal or permanent malfunction due to voltage drops or electromigrations. Multiple-valued current-mode (MVCM) integrated circuits have a potential advantage to reduce the wiring complexity and the nurnber of active devices in arithmetic large-scale-integration chips because the frequently used linear sum operation can be performed simply by wiring with no active devices. However, the switching speed in the MVCM circuit is relatively slow, and its power dissipation due to the steady current becomes high because current-sources in differential-pair circuits always flow a constant current in the active mode. In this project, a new MVCM circuit based on dual-rail differential logic has been proposed for high-speed,
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low-power, highly reliable arithmetic-oriented VLSI. A differential logic-style circuit has an attractive feature that its input voltage swing is small enough while maintaining a high currentdriving capability. The combination of the differential logic style and MVCM circuitry in arithmetic VLSI makes it possible to improve the switching speed compared with that of a corresponding binary CMOS implementation. Moreover, the use of a precharge-evaluate logic style abo makes the steady current flow cut off, which results in great reduction of dynamic power dissipation. A judicious combination of differential logic, MVCM logic and dynamic logic in the proposed circuit makes it possible to reduce the power dissipation together with device and interconnection counts while maintaining a high-speed switching capability. The use of dual-rail coding, which is used in differential logic-style circuit, is a widely used encoding style of asynchronous and self-checking circuit implementation. From this point of view, we have also proposed high-performance asynchronous and self-checking circuit using multiple-valued dual-rail complementary signals. Less
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