Fast and small area associative memories with minimum distance search capability
| Project/Area Number |
12838009
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
複合化集積システム
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| Research Institution | HIROSHIMA UNIVERSITY |
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Principal Investigator |
J Mattausch H Research Center for Nanodevices and Systems, HIROSHIMA UNIVERSITY, Professor, ナノデバイス研究センター, 教授 (20291487)
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| Co-Investigator(Kenkyū-buntansha) |
IWATA Atsushi Graduate School of Advanced Sciences of Matter, HIROSHIMA UNIVERSITY, Professor, 大学院・先端物質科学研究科, 教授 (30263734)
KOIDE Tetsushi Research Center for Nanodevices and Systems, HIROSHIMA UNIVERSITY, Associate Professor, ナノデバイス研究センター, 助教授 (30243596)
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| Project Period (FY) |
2000 – 2001
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| Project Status |
Completed (Fiscal Year 2001)
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| Budget Amount *help |
¥3,200,000 (Direct Cost: ¥3,200,000)
Fiscal Year 2001: ¥1,100,000 (Direct Cost: ¥1,100,000)
Fiscal Year 2000: ¥2,100,000 (Direct Cost: ¥2,100,000)
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| Keywords | Associative Memory / Hamming distance / Manhattan distance / CMOS technology / Recognition / Learning / CMOS集積回路 / 最小距離検索機能 / マンハタン距離 |
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| Research Abstract |
The purpose of this research project was to find a new architecture for integrating associative memories with short minimum-distance-search time and small area consumption in CMOS technology.
The target distance measures were the Hamming and the Manhattan distance.
Key result for achieving our objectives is the invention of a fully-parallel, combined digital/analog realization of the search function, whose complexity increases only linear with the number of reference pattern. In this way nearest-match-times < 100 ns have been realized for a reference-data base up to 128 pattern, each containing up to 768 equivalent bit. These high performance data, corresponding to a processing power of about 1 TOPS (Tera Operations Per Second), are achieved with a low power dissipation of only about 1-2 mW per reference pattern. The necessary silicon area is as small as < 10 mm^2 , even in a rather coarse 0.6 μm CMOS technology.
Implementation of the Hamming-distance search needs only 2 additional transistors to implement the EXNOR function for bit comparison between each bit of input pattern and stored reference pattern. Two alternative methods have been devised to realize the more complicated Manhattan distance search. The first method exploits the Hamming-distance-search hardware and implements the Manhattan distance by an encoding algorithm. The second method implements the necessary subtraction and absolute-value circuitry directly in the memory field for each binary of the reference pattern.
The research results achieved in this project have opened a new possibility for implementing the knowledge base of an intelligent system with recognition and learning capability, which has the potential of being superior to neural networks, because there is no restriction on the stored pattern type and new pattern learning can be realized by a simple write operation.
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Report
(3 results)
Research Products
(14 results)
