| Project/Area Number |
13305020
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| Research Category |
Grant-in-Aid for Scientific Research (A)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Electronic materials/Electric materials
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| Research Institution | HOKKAIDO UNIVERSITY |
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Principal Investigator |
HASEGAWA Hideki Hokkaido Univ., Graduate School of Eng., Prof., 大学院・工学研究科, 教授 (60001781)
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| Co-Investigator(Kenkyū-buntansha) |
AKAZAWA Masamichi Hokkaido Univ., Res.Center For Integrated Quantum Electronics, Associate Prof., 量子集積エレクトロニクス研究センター, 助教授 (30212400)
HASHIZUME Tamotsu Hokkaido Univ., Res.Center For Integrated Quantum Electronics, Associate Prof., 量子集積エレクトロニクス研究センター, 助教授 (80149898)
AMEMIYA Yoshihito Hokkaido Univ., Graduate School of Eng., Prof., 大学院・工学研究科, 教授 (80250489)
KASAI Seiya Hokkaido Univ., Graduate School of Eng., Associate Prof., 大学院・工学研究科, 助教授 (30312383)
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| Project Period (FY) |
2001 – 2003
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| Project Status |
Completed (Fiscal Year 2003)
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| Budget Amount *help |
¥55,380,000 (Direct Cost: ¥42,600,000、Indirect Cost: ¥12,780,000)
Fiscal Year 2003: ¥10,660,000 (Direct Cost: ¥8,200,000、Indirect Cost: ¥2,460,000)
Fiscal Year 2002: ¥16,250,000 (Direct Cost: ¥12,500,000、Indirect Cost: ¥3,750,000)
Fiscal Year 2001: ¥28,470,000 (Direct Cost: ¥21,900,000、Indirect Cost: ¥6,570,000)
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| Keywords | Single Electron Circuit / Binary Decision Diagram (BDD) / Hexagonal BDD Quantum Circuit / Quantum Dots / Schottky Gate / Quantum Wire Network / Power-Delay Product / Quantum Transport / ヘキサゴナルBDD量子回路 / ショットキーゲート |
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| Research Abstract |
The purpose of this research was to investigate a novel single electron integrated circuit based on a binary-decision diagram (BDD) architecture utilizing quantum dots controlled by nano-Schottky gates. Main results are listed below :
(1)A novel "hexagonal BDD quantum circuit approach" for realization of quantum LSIs, in which the BDD architecture is implemented on hexagonal nanowire network in high dense, was proposed. Various logic subsystems and arithmetic logic units (ALUs) were successfully designed utilizing the novel circuit approach.
(2)Elemental BDD devices (node devices) were realized using GaAs-based etched nanowires controlled by Schottky wrap gates (WPGs). They showed clear path switching characteristics from low temperature to room temperature. Power-delay product (PDP) of WPG-controlled single electron node devices was found to be as small as 10^<-22> J. Capability of GHz operation of WPG switches was confirmed experimentally by direct measurement of cut-off frequency.
(3)B
… More
asic BDD logic circuits were fabricated on etched hexagonal nanowire networks controlled by WPGs and they operated correctly in a quantum regime at low temperature. They were found to be possible to operate correctly even at room temperature by trading off of PDP values. Then, high-density integrated circuit fabrication process realizing 45 million devices/cm^2 has been established. Utilizing this process, 2-bit BDD adder circuits were fabricated and their correct operations were confirmed, and 8-bit adder was also successfully fabricated.
(4)Formation of hexagonal quantum nanowire network structures by MBE selective growth on patterned substrates was investigated and ultra-high density network fabrication technology of 240 million nodes/cm^2 for GaAs-based systems and 1 giga nodes/cm^2 for InP-based systems have been established. Branch switches and node devices were successfully fabricated utilizing the selectively MBE grown nanowires and their correct operations were confirmed.
(5)For surface passivation of III-V semiconductor quantum nanostructures, a technique using ultra-thin Si and c-GaN interface control layers (ICLs) was investigated for III-V materials and optimized. It was found that GaAs surfaces was successfully passivated by preparation of Ga-rich (4×6) reconstructed surface as an initial surface for the ICL formation. Ultra-small minimum interface state density of 4×10^<10> cm^<-2>eV^<-1> was obtained in the SiO_2/GaAs interface. Less
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