| Project/Area Number |
13440068
|
|---|
| Research Category |
Grant-in-Aid for Scientific Research (B)
|
| Allocation Type | Single-year Grants |
|---|
| Section | 一般 |
|---|
| Research Field |
素粒子・核・宇宙線
|
|---|
| Research Institution | The University of Tokyo |
|---|
Principal Investigator |
MASHIMO Tetsuro International Center for Elementary Particle Physics, associate professor, 素粒子物理国際研究センター, 助教授 (60181640)
|
|---|
| Co-Investigator(Kenkyū-buntansha) |
KUNO Yoshitaka Osaka University, Graduate School of Science, professor, 大学院・理学研究科, 教授 (30170020)
IMORI Masatoshi International Center for Elementary Particle Physics, research associate, 素粒子物理国際研究センター, 助手 (70011690)
|
|---|
| Project Period (FY) |
2001 – 2002
|
| Project Status |
Completed (Fiscal Year 2002)
|
| Budget Amount *help |
¥9,300,000 (Direct Cost: ¥9,300,000)
Fiscal Year 2002: ¥3,400,000 (Direct Cost: ¥3,400,000)
Fiscal Year 2001: ¥5,900,000 (Direct Cost: ¥5,900,000)
|
|---|
| Keywords | Domino Sampling Chip / DSC / Analog memoty / CMOS / free running mode / DRS |
|---|
| Research Abstract |
The goal of this research is to improve the Domino Sampling Chip (DSC), which is a CMOS fast analog memory chip developed at Paul Scherrer Institut (PSI) in Switzerland, and make a new chip which operates in a free running mode and has a ten times faster read out speed.
In tie first year of the project we concentrated on the design and fabrication of the basic standard circuit components using a 0.25 μm process technology: gate, comparator, voltage regulator, operational amplifier. For the DSC to operate in the free running mode, it is necessary to develop a circuit which circulates the domino wave. In the second year of the project, we actually produced the DSC which contains the circuit of tie circulating domino wave and allows us to read out at 40 MHz, and we did initial tests of the chip. The new chip has been named domino Ring Sampling Chip (DRS). The chip has 768 cells. The speed of the domino wave is controlled by an externally supplied voltage and is variable between 0.7 GHz and 2.4 GHz. The timing jitter of the domino wave per cycle was measured to be about 32 psec at 2.4 GHz, which demonstrates the stability of the domino wave. We also measured the temperature dependence of the speed (0.2%/ K) and the power consumption per channel (35 mW at 2.5 V and 6 mW at 1.8 V, where the maximum speed is reduced to 1.6 GHz in the latter case).
We will continue to test the chip focusing mainly on the read out circuit We also have a plan to design and fabricate a next generation of the DRS chip which will have 9 channels, 1024 cells per channel and other features.
|
