Grant-in-Aid for Scientific Research (C)
|Allocation Type||Single-year Grants |
|Research Institution||The University of Aizu |
KURODA Kenichi The Univ. of Aizu, Sch. Comp. Sci. & Eng., Prof., コンピュータ理工学部, 教授 (60285046)
SHIMA Masatoshi The Univ. of Aizu, Sch. Comp. Sci. & Eng., Prof., コンピュータ理工学部, 教授 (50325966)
OGURI Kiyoshi Nagasaki Univ., Dept. Eng., Prof., 工学部, 教授 (80325670)
|Project Period (FY)
2001 – 2002
Completed (Fiscal Year 2002)
|Budget Amount *help
¥3,600,000 (Direct Cost: ¥3,600,000)
Fiscal Year 2002: ¥1,400,000 (Direct Cost: ¥1,400,000)
Fiscal Year 2001: ¥2,200,000 (Direct Cost: ¥2,200,000)
|Keywords||asynchronous circuit / dynamical reconfiguration / plastic cell architecture|
Plastic cell architecture (PCA) is one of dynamically reconfigurable devices proposed by Prof. Oguri, one of the investigators. PCA has uniform fine grained structure with processing parts and memory parts and it is expected to be a breakthrough for the Von Neumann bottleneck between CPU-memories. This project aims to develop methodologies for circuit design and to survey applicable fields.
1) Development of Asynchronous Circuit Design Methodology on PCA
・ Prototyping process using software with hardware simulator was introduced to improve efficiency in asynchronous circuit design.
・ A library set including small size modules that are guaranteed to have no errors are established. These modules are connected by communicating paths and form larger scale asynchronous circuits. Based on the library, a lot of applications have been developed.
・ A simulation environment and a design methodology based on bit-serial processing were proposed.
・ A GUI layout tool and a verification tool were developed for improving design environment.
2) Design Languages for PCA
・ Semi-automatic conversion flow from HDL (SFL) to asynchronous circuits was proposed in order to utilize the conventional synchronous design resources in the past.
・ Hierarchical CDFGs and a dividing algorithm for the CDFG were proposed to create synthesizable STG from higher level specifications.
3) Device Structure for High Package Density
・LUT (look-up table) circuits for were investigated and two ways for high-speed operation were proposed.
4) Applications on PCA
・ In order to use reconfigurability, that is a feature of PCA, a vector processor, instruction-level parallel processor, serial multiplier. FIR filters were investigated.
・ Hardware implementation of artificial neural network was applied to PCA. Wire connection problem was solved by the use of dynamical wiring of PCA.