| Budget Amount *help |
¥3,100,000 (Direct Cost: ¥3,100,000)
Fiscal Year 2002: ¥1,500,000 (Direct Cost: ¥1,500,000)
Fiscal Year 2001: ¥1,600,000 (Direct Cost: ¥1,600,000)
|
|---|
| Research Abstract |
A new algorithm (I.e., a multi-step "breaking-off method" technique) has been developed. The new technique can reduce the amount of computation required to about 1/50 that of the conventional full-search algorithm, while it can maintain a mean absolute error (MAE), covsequently, a signal to noise ratio (SNR), at the same quantity as those of the full-search algorithm. This drastic reduction in the the amount of computation can reduce power dissipation of a motion estimator array by a factor of about 100,000.
The motion estimator, SRAM, CMOS image sensors, TEGs to investigate new low-power techniques, etc. have been designed, fabricated using 0.18 um CMOS technique. Their characteristics will be measured.
|
