| Project/Area Number |
13650409
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
情報通信工学
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| Research Institution | Osaka University |
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Principal Investigator |
HIGASHINO Teruo Grad. School Info. Sci. Tech. Professor, 大学院・基礎工学研究科, 教授 (80173144)
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| Co-Investigator(Kenkyū-buntansha) |
NAKATA Akio Grad. School Info. Sci. Assoc. Prof., 大学院・情報科学研究科, 助教授 (60295839)
YASUMOTO Eeiichi Nara. Inst. Sci. Tech. Assoc. Prof., 情報科学研究科, 助教授 (40273396)
FUNABIKI Nobuo Okayama Univ., Fac. Eng. Professor, 工学部, 教授 (70263225)
UMEDU Takaaki Grad. School Info. Sci. Assis. Prof., 大学院・情報科学研究科, 助手 (10346174)
YAMAGUCHI Hirozumi Grad. School Info. Sci. Assis. Prof., 大学院・情報科学研究科, 助手 (80314409)
北道 淳司 大阪大学, サイバーメディアセンタ, 講師 (20234271)
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| Project Period (FY) |
2001 – 2002
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| Project Status |
Completed (Fiscal Year 2002)
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| Budget Amount *help |
¥2,700,000 (Direct Cost: ¥2,700,000)
Fiscal Year 2002: ¥1,000,000 (Direct Cost: ¥1,000,000)
Fiscal Year 2001: ¥1,700,000 (Direct Cost: ¥1,700,000)
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| Keywords | Network Monitor / Network Management / Hardware Synthesis / Concurrent Systems / VHDL / Communication Protocols / Reliability / Multi-rendezvous |
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| Research Abstract |
Due to recent progress of the Internet, We need high-speed network monitors which can observe millions of packets per second. This research proposes a technique to synthesize hardware circuits from formal specifications of high-Speed network monitors described in LOTOS language.In the proposed method, a given network monitor is modeled as concurrent EFSMs, and data exchange among them is specified using multi-rendezvous in LOTOS. Depending on monitoring items and network speeds,We must derive different hardware circuits. For such parameter values, the proposed method can automatically select suitable hardware modules and adjust parameter values of the derived hardware component. We have developed a tool to generate the corresponding RT-level VHDL Specification from a given specification, and synthesize an FPGA circuit from the derived VHDL description. From our experiments, We have confirmed that the generated circuits have enough speeds for monitoring packets in Gigabit Ethernet.
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