| Budget Amount *help |
¥1,500,000 (Direct Cost: ¥1,500,000)
Fiscal Year 2002: ¥800,000 (Direct Cost: ¥800,000)
Fiscal Year 2001: ¥700,000 (Direct Cost: ¥700,000)
|
|---|
| Research Abstract |
CMOS technology is used for implamenting logic circuits. Open defects have often occurred in the circuits. However, open defects are hard to be detected. In this research, I attempted to develop test methods for delecting open defects, which occur in CMOS logic circuits. Since open defects in the CMOS circuit implemented on printed circuit boards can not be detected by the test method for detecting open defects in Ics, I made the following two kinds of studies.
1. Open defect detection method for CMOS Ics I proposed a test method based on supply current under time-varying electric field. Also, in order to detect open defects more easily, I proposed a test method based on supply current which flows when both time-varying electric field and supply voltage change are provided. Also, I proposed a test input generation method for the tests.
2. IC pin open detection method IC pin opens have often occurred when a CMOS logic circuit is fabricated on a printed circuit board. The opens are difficult to be detected. Any powerful test methods have not been proposed to detect them. Thus, I attempted to develop test methods to detect them. I proposed the following 3 kinds of test methods.
(1) test method based on supply current under a time-varying electric field, (2) test method based on supply current under a time-varying magnetic field, (3) power-off test method, which is based on current through protection diodes in CMOS Ics.
|
