Low-Power and High-Performance Processor based on Co-optimization of Architecture and Compiler
| Project/Area Number |
14380136
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
計算機科学
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| Research Institution | The University of Tokyo |
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Principal Investigator |
NAKAMURA Hiroshi The University of Tokyo, Research Center for Advanced Science and Technology, Associate Professor, 先端科学技術研究センター, 助教授 (20212102)
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| Co-Investigator(Kenkyū-buntansha) |
NANYA Takashi The University of Tokyo, Research Center for Advanced Science and Technology, Professor, 先端科学技術研究センター, 教授 (80143684)
SATO Mitsuhisa University of Tsukuba, Graduate School of Systems and Information Engineering, Professor, システム情報工学研究科, 教授 (60333481)
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| Project Period (FY) |
2002 – 2005
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| Project Status |
Completed (Fiscal Year 2005)
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| Budget Amount *help |
¥16,500,000 (Direct Cost: ¥16,500,000)
Fiscal Year 2005: ¥2,400,000 (Direct Cost: ¥2,400,000)
Fiscal Year 2004: ¥3,400,000 (Direct Cost: ¥3,400,000)
Fiscal Year 2003: ¥4,300,000 (Direct Cost: ¥4,300,000)
Fiscal Year 2002: ¥6,400,000 (Direct Cost: ¥6,400,000)
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| Keywords | Processor Architecture / Memory Hierarchy / Software Controlled Memory / Low Power Consumption / Compiler / Dynamic Power / Static Power / Register / 低消費電力プロセッサ / ダイナミック消費エネルギー / スタティック消費エネルギー / リーク電流 / 温度依存最適化 / レジスタファイル / 動的消費電力 / 静的消費電力 / 計算機アーキテクチャ / メモリシステム / マイクロプロセッサ / コンパイル技術 / キャッシュメモリ / 計算機アークテクチャ |
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| Research Abstract |
The purpose of this research is to achieve high performance and low power consumption by using compiler optimization on the usage of memory hierarchy. First, we proposed a new memory architecture which implements both software controlled memory and cache memory on a processor chip. By using the software controlled memory, compiler can optimize the data transfer between memory hierarchies and reduce power-wasting off-chip memory traffic. A new mechanism of register file is also proposed to reduce power consumption with little performance degradation. Second, we proposed a mechanism to shut down the voltage supply of the above new memory with fine granularity. Third, we developed a new compilation algorithm which co-operates with the above architecture for higher performance and lower power consumption. Energy consumption of a processor consists of dynamic energy and static energy. Because these two terms depend on the usage ration of software controlled memory independently, the least energy cannot be derived by minimizing either of them. Furthermore, static energy heavily depends on temperature. Thus, we propose a a new temperature aware compilation technique. The technique pre-computes the relationship between the memory usage ratio and operating temperature. Then, given source codes are optimized to select the best memory usage ratio dynamically by monitoring the operating temperature and by using the pre-computed relationship. We developed an environment to evaluate the effectiveness of our architecture and compilation algorithm. The evaluation results revealed that our co-optimization strategy can successfully reduce power consumption and achieve high performance.
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Report
(5 results)
Research Products
(31 results)
