• Search Research Projects
  • Search Researchers
  • How to Use
  1. Back to previous page

Three Dimensional Dapapath Synthesis for Nanotechnology VLSIs

Research Project

Project/Area Number 14550321
Research Category

Grant-in-Aid for Scientific Research (C)

Allocation TypeSingle-year Grants
Section一般
Research Field 電子デバイス・機器工学
Research InstitutionJapan Advanced Institute of Science and Technology

Principal Investigator

KANEKO Mineo  Japan Advanced Institute of Science and Technology, School of Information Science, Professor, 情報科学研究科, 教授 (00185935)

Project Period (FY) 2002 – 2003
Project Status Completed (Fiscal Year 2003)
Budget Amount *help
¥2,900,000 (Direct Cost: ¥2,900,000)
Fiscal Year 2003: ¥1,400,000 (Direct Cost: ¥1,400,000)
Fiscal Year 2002: ¥1,500,000 (Direct Cost: ¥1,500,000)
KeywordsVLSI design / Scheduling / resource binding / Layout design / Floorplan / Interconnection delay / RTL architecture / Design automation / VLSI / データパス合成 / RTレベルアーキテクチャ
Research Abstract

The objective of this research is to develop algorithms and software systems to design high performance VLSI systems in nanotechnology era, where the interconnection delay becomes a dominant factor to limit the operation speed of VLSI systems. Our key approach to such objective is the concurrent optimization of resource binding, scheduling and floorplan hardware modules. Our results include the following.
1.Binding driven scheduling : To consider interconnection delays during datapath synthesis, resource binding (i.e., assignment of operations to functional units, and variables to registers) and floorplan (i.e., location of each module in a layout area) must precede scheduling. Binding driven scheduling is so developed to solve timing assignment problem for a given resource binding and a floorplan.
2.Resource binding for minimizing the number of interconnections : The number of interconnections affects not only the amount of hardware but also electrical performance of the circuit. Focusing on the local similarity of the behavioral structure, a resource binding algorithm has been developed for designing RTL architecture with a reduced number of interconnections.
3.Control signal scheduling : An algorithm to design control signal schedule has been proposed, which can optimize the schedule under given signal transmission delay in datapath part and signal transmission delay from a controller to each module.
4.Application to asynchronous digital systems : Our binding driven scheduling algorithm has been modified for datapath design of asynchronous digital system, which is considered as one of promising technologies in nanotechnology era.
5.3-D datapath synthesis for reconfigurable systems : A coding system to represent solutions of 3-D datapath has been proposed, by which conventional searching method such as branch and bound, local search, simulated annealing, etc., can be applies to the concurrent binding, floorplan and scheduling problem.

Report

(3 results)
  • 2003 Annual Research Report   Final Research Report Summary
  • 2002 Annual Research Report
  • Research Products

    (24 results)

All 2004 2003 2002 Other

All Journal Article (14 results) Publications (10 results)

  • [Journal Article] Asynchronous Datapath Synthesis Based on Binding Space Exploration2004

    • Author(s)
      Koji Ohashi, Mineo Kaneko
    • Journal Title

      電子情報通信学会 第17回回路とシステム軽井沢ワークショップ論文集

      Pages: 549-554

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2003 Final Research Report Summary
  • [Journal Article] Asynchronous Datapath Synthesis Based on Binding Space Exploration2004

    • Author(s)
      Koji Ohashi, Mineo Kaneko
    • Journal Title

      Proceedings of the 17th Workshop on Circuits and Systems in Karuizawa

      Pages: 549-554

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2003 Final Research Report Summary
  • [Journal Article] 回路階層構造の動的再構築を伴う力学的手法に基づくフロアプラン合成2003

    • Author(s)
      小原正寛, 高島康裕, 金子峰雄
    • Journal Title

      電子情報通信学会VLSI設計技術研究会技術報告 VLD2002-148

      Pages: 13-18

    • NAID

      110003316144

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2003 Final Research Report Summary
  • [Journal Article] Binding Constrained Scheduling for Iterative Algorit hm with Conditional Branches2003

    • Author(s)
      Koji Ohashi, Mineo Kaneko
    • Journal Title

      Proceedings of the Workshop on Synthesis and System Integration of Mixed Information Technologies

      Pages: 144-151

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2003 Final Research Report Summary
  • [Journal Article] Post-Floorplan Control Schedule under Ma x/Min Logic/Interconnect Delays2003

    • Author(s)
      Mineo Kaneko, Koji Ohashi
    • Journal Title

      電子情報通信学会第16回回路とシステム軽井沢ワークショップ論文集

      Pages: 195-200

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2003 Final Research Report Summary
  • [Journal Article] 計算アルゴリズムの局所的類似性とそのデータパス合成への応用2003

    • Author(s)
      厚見吉彦, 大橋功治, 金子峰雄
    • Journal Title

      電子情報通信学会VLSI設計技術研究会技術報告 VLD2003-3

      Pages: 13-18

    • NAID

      110003294198

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2003 Final Research Report Summary
  • [Journal Article] 資源割り当て駆動スケジューリングにおけるレジスタ転送の自動挿入2003

    • Author(s)
      小畑貴之, 金子峰雄
    • Journal Title

      電子情報通信学会VLSI設計技術研究会技術報告 VLD2003-2

      Pages: 7-12

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2003 Final Research Report Summary
  • [Journal Article] Binding Constrained Scheduling for Iterative Algorithm with Conditional Branches2003

    • Author(s)
      Koji Ohashi, Mineo Kaneko
    • Journal Title

      Proceedings of the Workshop on Synthesis and System Integration of Mixed Information Technologies

      Pages: 144-151

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2003 Final Research Report Summary
  • [Journal Article] Post-Floorplan Control Schedule under Max/Min Logic/Interconnect Delays2003

    • Author(s)
      Mineo Kaneko, Koji Ohashi
    • Journal Title

      Proceedings of 16th Workshop on Circuits and Systems in Karuizawa

      Pages: 195-200

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2003 Final Research Report Summary
  • [Journal Article] Local Similarity in Computation Algorithm and Its Application to Data-path Synehsis2003

    • Author(s)
      Yoshihiko Atsumi, Koji Ohashi, Mineo Kaneko
    • Journal Title

      Technical Report of the Institute of Electronics, Information and Communication Engineers Vol.VLD2003-3

      Pages: 13-18

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2003 Final Research Report Summary
  • [Journal Article] Automatic Register to Register Transfer Insertion in Assignment Driven Scheduling2003

    • Author(s)
      Takayuki Obata, Mineo Kaneko, Satoshi Tayu
    • Journal Title

      Technical Report of the Institute of Electronics, Information and Communication Engineers Vol.VLD2003-2

      Pages: 7-12

    • NAID

      110003294197

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2003 Final Research Report Summary
  • [Journal Article] 幅制約モジュール配置問題のSAを用いた最適化手法2002

    • Author(s)
      田湯智, 金子峰雄
    • Journal Title

      電子情報通信学会VLSI設計技術研究会技術報告 VLD2002-100

      Pages: 109-114

    • NAID

      110003173553

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2003 Final Research Report Summary
  • [Journal Article] The Width Constrained Placement by the Simulated Annealing with the Sequence Pair Encoding2002

    • Author(s)
      Satoshi Tayu, Mineo Kaneko
    • Journal Title

      Technical Report of the Institute of Electronics, Information and Communication Engineers Vol.VLD2002-100

      Pages: 109-114

    • NAID

      110003173553

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2003 Final Research Report Summary
  • [Journal Article] Force-Directed Floorplan Synthesis with Rearrangement of Hierarchical Structure2002

    • Author(s)
      Masahiro Obara, Yasuhiro Takashima, Mineo Kaneko
    • Journal Title

      Technical Report of the Institute of Electronics, Information and Communication Engineers Vol.VLD2002-148

      Pages: 13-18

    • NAID

      110003316144

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2003 Final Research Report Summary
  • [Publications] Koji Ohashi, Mineo Kaneko: "Binding Constrained Scheduling for Iterative Algorithm with Conditional Branches"Proc.of the Workshop on Synthesis And System Integration of Mixed Information Technologies. 144-151 (2003)

    • Related Report
      2003 Annual Research Report
  • [Publications] Mineo Kaneko, Koji Ohashi: "Post-Floorplan Control Schedule under Max/Min Logic/Interconnect Delays"電子情報通信学会回路とシステム軽井沢ワークショップ. 195-200 (2003)

    • Related Report
      2003 Annual Research Report
  • [Publications] 小畑貴之, 金子峰雄, 田湯智: "資源割り当て駆動スケジューリングにおけるレジスタ間転送の自動挿入"電子情報通信学会VLSI設計技術研究会技術報告. VLD2003-2. 7-12 (2003)

    • Related Report
      2003 Annual Research Report
  • [Publications] 厚見吉彦, 大橋功治, 金子峰雄: "計算アルゴリズムの局所的類似性とそのデータパス合成への応用"電子情報通信学会VLSI設計技術研究会技術報告. VLD2003-3. 13-18 (2003)

    • Related Report
      2003 Annual Research Report
  • [Publications] Koji Ohashi, Mineo Kaneko: "Asynchronous Datapath Synthesis Based on Binding Space Exploration"電子情報通信学会回路とシステム軽井沢ワークショップ. (予定). (2004)

    • Related Report
      2003 Annual Research Report
  • [Publications] 田湯智, 金子峰雄: "幅制約モジュール配置問題のSAを用いた最適化手法"電子情報通信学会技術報告. VLD2002-100. 109-114 (2002)

    • Related Report
      2002 Annual Research Report
  • [Publications] 小原正寛, 高島康裕, 金子峰雄: "回路階層構造の動的再構築を伴う力学的手法に基づくフロアプラン合成"電子情報通信学会技術報告. VLD2002-148. 13-18 (2003)

    • Related Report
      2002 Annual Research Report
  • [Publications] Mineo Kaneko, Koji Ohashi: "Post-Floorplan Control Schedule under Max/Min Logic/Interconnect Delays"第16回回路とシステム(軽井沢)ワークショップ. (発表予定). (2003)

    • Related Report
      2002 Annual Research Report
  • [Publications] 厚見吉彦, 大橋功治, 金子峰雄: "計算アルゴリズムの局所的類似性とそのデータパス合成への応用"電子情報通信学会技術報告. (発表予定). (2003)

    • Related Report
      2002 Annual Research Report
  • [Publications] 小畑貴之, 金子峰雄, 田湯智: "資源割り当て駆動スケジューリングにおけるレジスタ間転送の自動挿入"電子情報通信学会技術報告. (発表予定). (2003)

    • Related Report
      2002 Annual Research Report

URL: 

Published: 2002-04-01   Modified: 2016-04-21  

Information User Guide FAQ News Terms of Use Attribution of KAKENHI

Powered by NII kakenhi