Three Dimensional Dapapath Synthesis for Nanotechnology VLSIs
| Project/Area Number |
14550321
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
電子デバイス・機器工学
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| Research Institution | Japan Advanced Institute of Science and Technology |
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Principal Investigator |
KANEKO Mineo Japan Advanced Institute of Science and Technology, School of Information Science, Professor, 情報科学研究科, 教授 (00185935)
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| Project Period (FY) |
2002 – 2003
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| Project Status |
Completed (Fiscal Year 2003)
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| Budget Amount *help |
¥2,900,000 (Direct Cost: ¥2,900,000)
Fiscal Year 2003: ¥1,400,000 (Direct Cost: ¥1,400,000)
Fiscal Year 2002: ¥1,500,000 (Direct Cost: ¥1,500,000)
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| Keywords | VLSI design / Scheduling / resource binding / Layout design / Floorplan / Interconnection delay / RTL architecture / Design automation / VLSI / データパス合成 / RTレベルアーキテクチャ |
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| Research Abstract |
The objective of this research is to develop algorithms and software systems to design high performance VLSI systems in nanotechnology era, where the interconnection delay becomes a dominant factor to limit the operation speed of VLSI systems. Our key approach to such objective is the concurrent optimization of resource binding, scheduling and floorplan hardware modules. Our results include the following.
1.Binding driven scheduling : To consider interconnection delays during datapath synthesis, resource binding (i.e., assignment of operations to functional units, and variables to registers) and floorplan (i.e., location of each module in a layout area) must precede scheduling. Binding driven scheduling is so developed to solve timing assignment problem for a given resource binding and a floorplan.
2.Resource binding for minimizing the number of interconnections : The number of interconnections affects not only the amount of hardware but also electrical performance of the circuit. Focusing on the local similarity of the behavioral structure, a resource binding algorithm has been developed for designing RTL architecture with a reduced number of interconnections.
3.Control signal scheduling : An algorithm to design control signal schedule has been proposed, which can optimize the schedule under given signal transmission delay in datapath part and signal transmission delay from a controller to each module.
4.Application to asynchronous digital systems : Our binding driven scheduling algorithm has been modified for datapath design of asynchronous digital system, which is considered as one of promising technologies in nanotechnology era.
5.3-D datapath synthesis for reconfigurable systems : A coding system to represent solutions of 3-D datapath has been proposed, by which conventional searching method such as branch and bound, local search, simulated annealing, etc., can be applies to the concurrent binding, floorplan and scheduling problem.
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Report
(3 results)
Research Products
(24 results)
