ゲルマニウム／ひずみーシリコンヘテロ接合を用いたトンネル電界効果トランジスタ
| Project/Area Number |
14J06072
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| Research Category |
Grant-in-Aid for JSPS Fellows
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| Allocation Type | Single-year Grants |
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| Section | 国内 |
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| Research Field |
Electron device/Electronic equipment
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| Research Institution | The University of Tokyo |
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Principal Investigator |
金 ミンス 東京大学, 工学系研究科, 特別研究員(PD)
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| Project Period (FY) |
2014-04-25 – 2016-03-31
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| Project Status |
Completed (Fiscal Year 2015)
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| Budget Amount *help |
¥2,170,000 (Direct Cost: ¥1,900,000、Indirect Cost: ¥270,000)
Fiscal Year 2015: ¥1,170,000 (Direct Cost: ¥900,000、Indirect Cost: ¥270,000)
Fiscal Year 2014: ¥1,000,000 (Direct Cost: ¥1,000,000)
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| Keywords | Tunnel FET / Ge-source / Back biasing / Strain Engineering / MOS interface |
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| Outline of Annual Research Achievements |
1. Back biasing effect
Positive VB yields a significant increase in Ion and decrease in SS in a wide range of middle ID region in spite of the increase in Ioff. Negative VB is attributable to the suppressed tunneling current, resulting in lower SSmin. It is revealed that tunneling current, especially vertical tunneling can occur from Ge-source to back interface of sSi-channel and current can flow through the inversion layer formed near back interface of sSi-channel. This vertical tunneling current shows high drain on current than lateral tunneling current because of high tunneling efficiency and these vertically tunneled electrons make an n-source at beneath the Ge-source and near back interface of sSi channel. However, the sSi channel is mainly controlled by VG because of much thinner EOT of front gate insulators than that of BOX. Consequently, this positive VB-induced vertical tunneling is greatly promising to improve the performance of Ge/sSi TFETs and it can be effectively utilized for improving the TFET performance by applying the synchronized VB with VG in multi-gate structure such as Fin FET, nanowire and so on.
2. Drain engineering
It is experimentally confirmed that the modified drain doping concentration of 1018 cm-3 is suitable for further performance improvement.
3. EOT scaling
In this study the EOT was scaling from 2.5 nm to 1.5 nm by changing the gate dielectric material from Al2O3 to HfO2. It is found that higher on current is obtained in thinner EOT device. However, the leakage current increases in HfO2-device because of large Dit with Ge and Si.
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| Research Progress Status |
27年度が最終年度であるため、記入しない。
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| Strategy for Future Research Activity |
27年度が最終年度であるため、記入しない。
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Report
(2 results)
Research Products
(8 results)
