Virtual Hardware Mechanism for dynamically reconfigurable devices
| Project/Area Number |
15300022
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Computer system/Network
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| Research Institution | KEIO UNIVERSITY |
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Principal Investigator |
AMANO Hideharu Keio Univ., Faculty of Science and Technology, Professor, 理工学部, 教授 (60175932)
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| Co-Investigator(Kenkyū-buntansha) |
OGURI Kiyoshi Nagasaki Univ., Faculty of Engineering, Professor, 工学部, 教授 (80325670)
SHIBATA Yuuichiro Nagasaki Univ., Faculty of Engineering, Assistant Professor, 工学部, 教授 (10336183)
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| Project Period (FY) |
2003 – 2005
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| Project Status |
Completed (Fiscal Year 2005)
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| Budget Amount *help |
¥9,600,000 (Direct Cost: ¥9,600,000)
Fiscal Year 2005: ¥700,000 (Direct Cost: ¥700,000)
Fiscal Year 2004: ¥3,900,000 (Direct Cost: ¥3,900,000)
Fiscal Year 2003: ¥5,000,000 (Direct Cost: ¥5,000,000)
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| Keywords | Reconfigurable System / Virtual Hardware / Dynamic reconfiguration / Network on Chip / Multicontext reconfigurable devices / Dynamic Reconfiguration / Network On Chip / Multicontext Devices / Multicontext Reconfigurable Devices / Dynamic Adaptive Hardware / Dynamic Reconfigurable Processor / Multicontext Device |
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| Research Abstract |
1.Various types of streaming application were implemented on NEC electronics' dynamically reconfigurable processor DRP-1, and the primary trade-off for introducing virtual hardware mechanism was evaluated. Through the evaluation, the area-efficiency is improved from 4 times to 14 times by introducing the dynamic reconfiguration.
2.Using the virtual hardware mechanism, (1)Adaptive IPsec system and (2)Adaptive Viterbi decoder are implemented on DRP-1. In the adaptive IPsec system, multiple decryption hardware modules are changed on demand. Using this mechanism, a complicated system can be implemented on a small cost. In the adaptive Viterbi decoder, several designs with various constraint variable Ks are changed in response to the S/N ratio. Using this mechanism, the power consumption becomes a half.
3.Input/Output mechanisms are proposed for efficient implementation of the virtual hardware mechanism.
4.The on chip network and interconnection method to connect processors in dynamically reconfigurable systems were investigated. For efficient implementation of the virtual hardware, a new packet transfer mechanism called Black-bus was proposed. Also, a new topology called Fat-H-Tree was proposed.
5.In order to implement the virtual hardware efficiently, a high speed reconfiguration is required. For this purpose, a template configuration which can reduce both the loading time and context memory is proposed. Also, a multicast reconfiguration method called RoMulTic was proposed.
These research results were presented in FPL,ICFPL, and FCCM : representative international conference on reconfigurable systems every year from 2003-2005. A keynote speech on dynamically reconfigurable processors is invited on the Digital Convergence 2004 which was held in Singapole. One of the journal papers received the best paper award of IEICE Transaction in 2004, and a presentation in SACSIS2006 received outstanding young researcher award
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Report
(4 results)
Research Products
(23 results)
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[Book] オーム社2005
Author(s)
末吉敏則, 天野英晴
Total Pages
278
Publisher
リコンフィギャラブルシステム
Description
「研究成果報告書概要(和文)」より
Related Report
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