Self assembly of quantum dot and application to electron device using bio-nano process
| Project/Area Number |
15360191
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Electron device/Electronic equipment
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| Research Institution | Nara Institute of Science and Technology |
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Principal Investigator |
FUYUKI Takashi Nara Institute of Science and Technology, Graduate School of Materials Science, Professor, 物質創成科学研究科, 教授 (10165459)
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| Co-Investigator(Kenkyū-buntansha) |
URAOKA Yukiharu Nara Institute of Science and Technology, Graduate School of Materials Science, Associate Professor, 物質創成科学研究科, 助教授 (20314536)
HATAYAMA Tomoaki Nara Institute of Science and Technology, Graduate School of Materials Science, Assistant Professor, 物質創成科学研究科, 助手 (90304162)
YANO Hiroshi Nara Institute of Science and Technology, Graduate School of Materials Science, Assistant Professor, 物質創成科学研究科, 助手 (40335485)
YAMASHITA Ichiro Matsushita Advanced Technology Research Laboratories, Senior Engineer, 先端技術研究所, 主幹技師
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| Project Period (FY) |
2003 – 2004
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| Project Status |
Completed (Fiscal Year 2004)
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| Budget Amount *help |
¥15,100,000 (Direct Cost: ¥15,100,000)
Fiscal Year 2004: ¥6,700,000 (Direct Cost: ¥6,700,000)
Fiscal Year 2003: ¥8,400,000 (Direct Cost: ¥8,400,000)
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| Keywords | Bio-nano process / self assemble / bottom-up / bio-mineralization / Quntum dot / floating gate transistor / フェリチンタンパク / フローティグゲートトランジスタ |
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| Research Abstract |
Si nano-crystal dot is investigated for the wide usage of quantum device. The feature of the Si nano-crystal dot is the compatibility with the conventional Si process and their simple fabrication techniques. As the most promising application of the Si nano-crystal dot, floating gate memory is proposed in several works. It is reported that the Si dot is applicable to the memory devices. The feature of the nano-crystal dot memory is their extreme high reliability to the tunnel oxide breakdown. Even if the oxide is broken down locally, this does not lead to the failure of whole device performance.
In this work, we propose a new deposition technique using side-wall typed plasma-enhanced CVD(PECVD). This method provides Si nano-crystal morphology at low temperature (430℃) and the damage of tunnel oxide was lower than parallel plate typed CVD. We have successfully developed the Si nano-crystal dot fabricated by PECVD for the first time. We have fabricated a floating gate memory using Si nano-crystal dot employing the CVD technique at low temperature. In order to analyze the electron behavior, we employed the thin tunnel oxide with a thickness of 3 nm. We have successfully confirmed the charging and discharging effect in the dot of n-channel metal-oxide-semiconductor-field effect transistor (MOSFET).
Furthermore, we proposed to use the core of ferritin protein as floating gate. Initially, the core is ferric oxide, therefore, reduction of the core is necessary. We investigate the reduction method of the core to conductive by embedding the core in the amorphous silicon. XPS signal revealed that the core was successfully changed from Fe2O3 to Fe.
This study provides the new technique for fabricating new memory device in the future.
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Report
(3 results)
Research Products
(19 results)
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[Journal Article] Electron Injection into Si nano dot fabricated by Side-wall type plasma enhanced chemical vapor deposition2005
Author(s)
Kazunori Ichikawa, Masato Mukai, P.Punchaipetch, Hiroshi Yano, Tomoaki Hatayama, Yukiharu Uraoka, Takashi Fuyuki, Eiji Takahashi, Tsukasa Hayashi, Kiyoshi Ogata
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Journal Title
IEEE/International Meeting for Future Electron Devices, Kansai P-D7
Pages: 97-97
Description
「研究成果報告書概要(欧文)」より
Related Report
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