Design of a Gigabit RSA encryption processor based on redundant binary arithmetic
| Project/Area Number |
15500050
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Computer system/Network
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| Research Institution | Hacinohe Institute of Technology |
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Principal Investigator |
TOMABECHI Nobuhiro Hachinohe Institute of Technology, Faculty of Engineering, Professor, 工学部, 教授 (70048180)
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| Project Period (FY) |
2003 – 2004
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| Project Status |
Completed (Fiscal Year 2004)
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| Budget Amount *help |
¥1,900,000 (Direct Cost: ¥1,900,000)
Fiscal Year 2004: ¥700,000 (Direct Cost: ¥700,000)
Fiscal Year 2003: ¥1,200,000 (Direct Cost: ¥1,200,000)
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| Keywords | RSA cryptosystem / Processor / Design / Redundant binary number / Table-look-up / Pipeline / Gigabit / 高速 / 冗長2進数 |
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| Research Abstract |
(1)Design of pipeline architectures
To enhance the operation speed o four RSA encryption processor based on redundant binary arithmetic and table-look-up, the introduction of pipelined architectures has been studied. Three architectures are presented as follows.
A.Architecture combining a binary tree structure of adders with a pipelined structure:
In this structure, a part of the binary tree structure of adders is taken as a pipelined unit, and the units are sequentially connected in the form of a pipelined structure. By this structure, a higher speed encryption can be realized for both discontinuous and continuous input by slight modification of the prior architecture.
B.Reconfigurable architecture:
In this architecture, the binary tree structure is formed only for discontinuous input, and the pipelined structure is formed only for continuous input in turn. By this architecture, the best structure can be applied to both discontinuous and continuous input.
C.Architecture applying pipelined operation to 2N cycle operations:
In this structure, the pipelined operation is applied to the 2N cycle repetition ofmultiplication and residue calculation in the RSA encryption algorithm. By this architecture, the highest speed encryption can be realized because pipelined operation is fully applied to all over the RSA encryption operations if a VLSI chip with an extremely high integration can be used.
(2)Experiments on the remote control using Japan Gigabit Network
An experimental system for video image transfer via a part of Japan Gigabit Network is constructed. Using this system, the average delay time for single packet transfer is made clear.
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Report
(3 results)
Research Products
(15 results)
