Research on retargetable code generation for custom VLIW DSPs
| Project/Area Number |
15500055
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Computer system/Network
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| Research Institution | Kwansei Gakuin University |
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Principal Investigator |
ISHIURA Nagisa Kwansei Gakuin University, School of Science and Technology, Professor, 理工学部, 教授 (60193265)
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| Co-Investigator(Kenkyū-buntansha) |
TAKAHASHI Kazuko Kwansei Gakuin University, School of Science and Technology, Associate Professor, 理工学部, 助教授 (30330400)
MIWA Hiroyoshi Kwansei Gakuin University, School of Science and Technology, Lecturer, 理工学部, 講師 (40351738)
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| Project Period (FY) |
2003 – 2004
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| Project Status |
Completed (Fiscal Year 2004)
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| Budget Amount *help |
¥3,700,000 (Direct Cost: ¥3,700,000)
Fiscal Year 2004: ¥1,500,000 (Direct Cost: ¥1,500,000)
Fiscal Year 2003: ¥2,200,000 (Direct Cost: ¥2,200,000)
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| Keywords | Retargetable Compiler / VLIW Architecture / DSP / Custom Processor / ASIP Meister / Embedded System |
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| Research Abstract |
In this project, we have attempted to develop a retargetable compiler for "ASIP Meister" processor synthesis system, which have been developed at Osaka University, and to design new algorithms for code scheduling, with a view to establish an efficient retargetable compilation method.
We examined the processor specification language and the underlying VLIW processor model of the ASIP-Meister system, so as to design a data structure called an operation table which summarizes the processor information necessary for retargetable code generation. One of the major technical contributions is a method of generating a set of the instruction patterns from behavioral description of the instruction set, in which instruction patterns that are necessary for compilers but are not explicitly described in the specification are automatically generated. Another contribution is extraction of the operation latencies from processor specifications. We have developed a method of computing operation latencies in the presence of pipeline forwarding, for all the RAW, WAR, and WAW dependencies. This is based on a way of specifying forwarding using forwarding units and formalization of correct and complete forwarding.
As for a code scheduling algorithm, we focused on exact methods based on symbolic state traversal and Boolean satisfiability. As well as extending those methods so that multicycle and pipelined computation units can be handled, we have developed a framework of using a pseudo-Boolean satisfiability solver. It can directly deal with pseudo-Boolean constraints, i.e.linear inequalities, and thus contributes to speeding up of code generation.
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Report
(3 results)
Research Products
(7 results)
