Moving Picture Codec LSI for High Definition TVs
| Project/Area Number |
15560306
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Electron device/Electronic equipment
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| Research Institution | CHUO UNIVERSITY |
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Principal Investigator |
ENOMOTO Tadayoshi Chuo University, Faculty of Science and Engineering, Professor, 理工学部, 教授 (10245988)
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| Project Period (FY) |
2003 – 2004
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| Project Status |
Completed (Fiscal Year 2004)
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| Budget Amount *help |
¥3,700,000 (Direct Cost: ¥3,700,000)
Fiscal Year 2004: ¥1,800,000 (Direct Cost: ¥1,800,000)
Fiscal Year 2003: ¥1,900,000 (Direct Cost: ¥1,900,000)
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| Keywords | LSI / prosessor / power disspation / low power techniqe / leakage current / motion estimation algorithm / moving picture encoding / breaking off search algorithm / 固体撮像素子 / 高性能化技術 |
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| Research Abstract |
(1) Related technologies for this research such as moving picture encoding and decoding, high speed signal processing, low-power and low-leakages current for LSIs, etc have been investigated.
(2) High speed motion vector estimation methods such as "multi-step breaking off search algorithm" etc. have been developed. To reduce power dissipation of an absolute difference accumulator (ADA) for motion estimation (NIE), a fast ME algorithm called a "Breaking-Off Search Adaptively minimizing number of block matchings (BOSA)" algorithm was developed. BOSA can improve processing speed of the full-search (FS) method by a factor of more than 10, while maintaining visual quality of the FS method.
(3) At clock frequency of 160 MHz and supply voltage of 1.4 V the power dissipation of a 0.18-μm CMOS absolute difference accumulator (ADA) using BOSA and a gated-clock pulse scheme was reduced to 30 μW that was about 1/1,000,000 that of the same ADA implementing FS.
(4) In order to reduce leakage current, a self-controllable voltage level (SVL) circuit, which can supply a maximum DC voltage to an active-load circuit on request or can decrease the DC voltage supplied to a load circuit in stand-by mode, was developed. This SVL circuit can drastically reduce stand-by leakage power of CMOS logic circuits and SRAMs with minimal overheads in terms of chip area and speed. The stand-by power of 1-Kb SRAM incorporating the SVL circuit was 65.7 nW that was about 20 % of that (321 nW) of an equivalent conventional 1-Kbit SRAM. The active power of this new SRAM was 625 μW, 95 % of that of the equivalent conventional 1-Kbit SRAM (at VDD = 1.8 V, fc = 100 MHz). The read-access time of this new SRAM was 553 psec, that is, only 2.6% longer than that of the equivalent conventional 1-Kb SRAM.
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Report
(3 results)
Research Products
(26 results)
