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Low voltage operation of new functional circuits by a silicon single electron transistor and CMOS at room temperature

Research Project

Project/Area Number 15H02247
Research Category

Grant-in-Aid for Scientific Research (A)

Allocation TypeSingle-year Grants
Section一般
Research Field Electron device/Electronic equipment
Research InstitutionThe University of Tokyo

Principal Investigator

Hiramoto Toshiro  東京大学, 生産技術研究所, 教授 (20192718)

Project Period (FY) 2015-04-01 – 2019-03-31
Project Status Completed (Fiscal Year 2019)
Budget Amount *help
¥43,810,000 (Direct Cost: ¥33,700,000、Indirect Cost: ¥10,110,000)
Fiscal Year 2018: ¥9,360,000 (Direct Cost: ¥7,200,000、Indirect Cost: ¥2,160,000)
Fiscal Year 2017: ¥9,360,000 (Direct Cost: ¥7,200,000、Indirect Cost: ¥2,160,000)
Fiscal Year 2016: ¥11,700,000 (Direct Cost: ¥9,000,000、Indirect Cost: ¥2,700,000)
Fiscal Year 2015: ¥13,390,000 (Direct Cost: ¥10,300,000、Indirect Cost: ¥3,090,000)
Keywords半導体物性 / 大規模集積回路 / MOSFET / Beyond CMOS / 単電子トランジスタ
Outline of Final Research Achievements

This research aims at the low voltage operation of integrated circuits by beyond CMOS and conventional CMOS circuits. The low voltage circuits consist of silicon nanowire transistors, and a room temperature operating single electron transistor is adopted as beyond CMOS. The gate voltage of the Coulomb oscillation peak is as low as 0.45V and the supply voltage of nanowire transistor circuits is 2V. The tiny current of the Coulomb oscillations was amplified and converted to the amplitude of 0.8V by the current-voltage conversion circuits. From the results, the low voltage operation of integrated circuits by room temperature operating single electron transistor and conventional MOS transistors has been demonstrated.

Academic Significance and Societal Importance of the Research Achievements

トランジスタの微細化による従来の大規模集積回路の性能向上が困難になりつつある状況において,従来デバイスと異なる原理で動作するいわゆるBeyond CMOSの研究が進んでいるが,従来のMOS回路との融合に関する研究は,その作製が困難なことからほとんど進んでこなかった.今回,室温動作の単電子トランジスタとナノワイヤトランジスタによる融合回路の低電圧動作が示されたことで,将来の集積エレクトロニクスの新しい方向性が実証されたということができ,学術的意義および社会的意義は大きい.

Report

(5 results)
  • 2019 Final Research Report ( PDF )
  • 2018 Annual Research Report
  • 2017 Annual Research Report
  • 2016 Annual Research Report
  • 2015 Annual Research Report
  • Research Products

    (13 results)

All 2020 2018 2016 2015

All Presentation (13 results) (of which Int'l Joint Research: 7 results)

  • [Presentation] Integrated Circuits Composed of Nanowire and Single-Electron Transistors Operating at Room Temperature2020

    • Author(s)
      Tomoko Mizutani
    • Organizer
      IEEE Silicon Nanoelectronics Workshop
    • Related Report
      2018 Annual Research Report
    • Int'l Joint Research
  • [Presentation] 微細ゲートオールアラウンド(GAA)シリコンナノワイヤトランジスタにおける極めて大きなランダムテレグラフノイズ(RTN)の解析2020

    • Author(s)
      木村迅利
    • Organizer
      第67回応用物理学会春季学術講演会
    • Related Report
      2018 Annual Research Report
  • [Presentation] Detection of Charge Traps in Silicon Nanowire MOSFETs Using Transient Current Measurements2020

    • Author(s)
      Boyang Cui
    • Organizer
      第67回応用物理学会春季学術講演会
    • Related Report
      2018 Annual Research Report
  • [Presentation] Statistics of Random Telegraph Noise Amplitude in Extremely Narrow Silicon Nanowire Transistors with Width down to 2nm2018

    • Author(s)
      Toshiro Hiramoto
    • Organizer
      International Conference on Nanoelectronics Strategy (INS)
    • Related Report
      2018 Annual Research Report
    • Int'l Joint Research
  • [Presentation] Drain-Induced Variability Due to Quantum Confinement Effect in Extremely Narrow Silicon Nanowire Transistors with Width down to 2nm2018

    • Author(s)
      Toshiro Hiramoto
    • Organizer
      International Conference on Nanoelectronics Strategy (INS)
    • Related Report
      2018 Annual Research Report
    • Int'l Joint Research
  • [Presentation] Enhanced Variability by Quantum Confinement Effects in Extremely Narrow Silicon Nanowire MOSFETs with Nanowire Width down to 2nm2016

    • Author(s)
      Toshiro Hiramoto
    • Organizer
      12th International Nanotechnology Conference on Communication and Cooperation (INC12)
    • Place of Presentation
      Leuven, Belgium
    • Related Report
      2016 Annual Research Report
    • Int'l Joint Research
  • [Presentation] Increased Drain-Induced Variability and Within-Device Variability in Extremely Narrow Silicon Nanowire MOSFETs with Width down to 2nm2016

    • Author(s)
      Tomoko Mizutani, Kiyoshi Takeuchi, Ryota Suzuki, Takuya Saraya, Masaharu Kobayashi, and Toshiro Hiramoto
    • Organizer
      IEEE Silicon Nanoelectronics Workshop
    • Place of Presentation
      Hilton Hawaiian Village, Honolulu, HI. USA
    • Related Report
      2016 Annual Research Report
    • Int'l Joint Research
  • [Presentation] 線幅2nmの超微細シリコンナノワイヤトランジスタにおけるDIBLばらつきおよびデバイス内ばらつき2016

    • Author(s)
      水谷朋子,竹内 潔,鈴木龍太,更屋拓哉,小林正治,平本俊郎
    • Organizer
      電子情報通信学会シリコン材料・デバイス研究会(SDM)
    • Place of Presentation
      中央電気倶楽部(大阪府)
    • Related Report
      2016 Annual Research Report
  • [Presentation] 線幅2nmの超微細シリコンナノワイヤトランジスタにおけるドレイン電圧に起因する特性ばらつき2016

    • Author(s)
      水谷朋子,竹内 潔,鈴木龍太,更屋拓哉,小林正治,平本俊郎
    • Organizer
      第77回応用物理学会秋季学術講演会
    • Place of Presentation
      朱鷺メッセ(新潟県)
    • Related Report
      2016 Annual Research Report
  • [Presentation] Threshold Voltage and Current Variability of Extremely Narrow Silicon Nanowire MOSFETs with Width down to 2nm2015

    • Author(s)
      T. Mizutani, Y. Tanahashi, R. Suzuki, T. Saraya, M. Kobayashi, and T. Hiramoto
    • Organizer
      Silicon Nanoelectronics Workshop
    • Place of Presentation
      Rihga Royal Hotel Kyoto, Kyoto
    • Related Report
      2015 Annual Research Report
    • Int'l Joint Research
  • [Presentation] Characteristics of Silicon Nanowire Transistors for Integration with Room-Temperature Operating Silicon Single-Electron Transistors2015

    • Author(s)
      T. Hiramoto
    • Organizer
      Sweden-Japan QNANO Workshop
    • Place of Presentation
      Hindas, Sweden
    • Related Report
      2015 Annual Research Report
    • Int'l Joint Research
  • [Presentation] 線幅2nmの超微細シリコンナノワイヤトランジスタにおけるしきい値電圧および電流ばらつき2015

    • Author(s)
      水谷朋子,棚橋裕麻,鈴木龍太,更屋拓哉,小林正治,平本俊郎
    • Organizer
      電子情報通信学会 シリコン材料・デバイス研究会
    • Place of Presentation
      熊本市民会館崇城大学ホール(熊本県)
    • Related Report
      2015 Annual Research Report
  • [Presentation] 線幅2nmの超微細シリコンナノワイヤトランジスタにおける量子閉じ込め効果によるしきい値電圧および電流ばらつき2015

    • Author(s)
      水谷朋子,棚橋裕麻,鈴木龍太,更屋拓哉,小林正治,平本俊郎
    • Organizer
      第76回応用物理学会秋季学術講演会
    • Place of Presentation
      名古屋国際会議場(愛知県)
    • Related Report
      2015 Annual Research Report

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Published: 2015-04-16   Modified: 2022-11-04  

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