Hardware Synthesis from OpenCL Programs
| Project/Area Number |
15H02680
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Computer system
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| Research Institution | Ritsumeikan University |
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Principal Investigator |
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| Co-Investigator(Kenkyū-buntansha) |
谷口 一徹 大阪大学, 情報科学研究科, 准教授 (40551453)
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| Research Collaborator |
Dutt Nikil
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| Project Period (FY) |
2015-04-01 – 2019-03-31
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| Project Status |
Completed (Fiscal Year 2018)
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| Budget Amount *help |
¥15,990,000 (Direct Cost: ¥12,300,000、Indirect Cost: ¥3,690,000)
Fiscal Year 2018: ¥3,640,000 (Direct Cost: ¥2,800,000、Indirect Cost: ¥840,000)
Fiscal Year 2017: ¥3,640,000 (Direct Cost: ¥2,800,000、Indirect Cost: ¥840,000)
Fiscal Year 2016: ¥4,160,000 (Direct Cost: ¥3,200,000、Indirect Cost: ¥960,000)
Fiscal Year 2015: ¥4,550,000 (Direct Cost: ¥3,500,000、Indirect Cost: ¥1,050,000)
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| Keywords | LSI設計技術 / 並列処理 / 設計自動化 |
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| Outline of Final Research Achievements |
We have developed multi/manycore architectures which efficiently execute parallel applications written in OpenCL. The developed architectures are customizable for the given applications. We have implemented the architectures on FPGA boards and evaluated their performance by actually executing a set of applications on the FPGA boards. We have also developed techniques for mapping and scheduling parallel tasks on multi/manycore architectures.
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| Academic Significance and Societal Importance of the Research Achievements |
近年、CPUコア単体の性能は頭打ちになっており、汎用計算機だけでなく組込みシステムにおいても、複数または多数のCPUコアを搭載したマルチコア／メニーコア・アーキテクチャが普及している。本研究の社会的な意義は、高性能で安価なマルチコア／メニーコア組込みシステムを短期間で設計することを可能とすることである。一方、学術的には、可変な並列度を持つタスクのスケジューリングに関して、理論的な基礎を確立した。
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Report
(5 results)
Research Products
(71 results)
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[Presentation] 配列型近似乗算器の設計と解析2016
Author(s)
山元貴普, 谷口一徹, 冨山宏之, 山下茂, 原祐子
Organizer
回路とシステムワークショップ
Place of Presentation
北九州国際会議場（福岡県・北九州市）
Year and Date
2016-05-13
Related Report
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