A research on a heterogeneous multicore that enables flexible cooperation among CPUs, accelerators and data transfer units on a chip
| Project/Area Number |
15K00085
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Multi-year Fund |
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| Section | 一般 |
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| Research Field |
Computer system
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| Research Institution | Waseda University |
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Principal Investigator |
Kimura Keiji 早稲田大学, 理工学術院, 教授 (50318771)
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| Project Period (FY) |
2015-04-01 – 2018-03-31
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| Project Status |
Completed (Fiscal Year 2017)
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| Budget Amount *help |
¥4,680,000 (Direct Cost: ¥3,600,000、Indirect Cost: ¥1,080,000)
Fiscal Year 2017: ¥1,690,000 (Direct Cost: ¥1,300,000、Indirect Cost: ¥390,000)
Fiscal Year 2016: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000)
Fiscal Year 2015: ¥1,690,000 (Direct Cost: ¥1,300,000、Indirect Cost: ¥390,000)
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| Keywords | ヘテロジニアスマルチコア / 自動並列化コンパイラ / アクセラレータ / マルチコア / 並列化コンパイラ |
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| Outline of Final Research Achievements |
We developed a heterogeneous multicore architecture and its compiler flow, which enable flexible cooperation among CPUs, accelerator cores, and data transfer units, which is a kind of extended DMA controller, in a multicore chip. One of the main achievements in this research project is that a program parallelized by the developed compiler flow including LLVM backend for the accelerator core obtains 24.91x speedup on the heterogeneous multicore on an FPGA test bed, which is also developed in this research.
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Report
(4 results)
Research Products
(11 results)
