| Project/Area Number |
16206037
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| Research Category |
Grant-in-Aid for Scientific Research (A)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Electron device/Electronic equipment
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| Research Institution | Keio University |
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Principal Investigator |
KURODA Tadahiro Keio Univ., Faculty of Science and Tech., Professor, 理工学部, 教授 (50327681)
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| Co-Investigator(Kenkyū-buntansha) |
AMANO Hideharu Keio Univ., Faculty of Science and Tech., Professor, 理工学部, 教授 (60175932)
MAKABE Toshiaki Keio Univ., Faculty of Science and Tech., Professor, 理工学部, 教授 (60095651)
NAKANO Nobuhiko Keio Univ., Faculty of Science and Tech., Assoc Professor, 理工学部, 助教授 (40286638)
SANADA Yukitoshi Keio Univ., Faculty of Science and Tech., Assoc. Professor, 理工学部, 助教授 (90293042)
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| Project Period (FY) |
2004 – 2006
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| Project Status |
Completed (Fiscal Year 2006)
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| Budget Amount *help |
¥47,970,000 (Direct Cost: ¥36,900,000、Indirect Cost: ¥11,070,000)
Fiscal Year 2006: ¥8,580,000 (Direct Cost: ¥6,600,000、Indirect Cost: ¥1,980,000)
Fiscal Year 2005: ¥7,800,000 (Direct Cost: ¥6,000,000、Indirect Cost: ¥1,800,000)
Fiscal Year 2004: ¥31,590,000 (Direct Cost: ¥24,300,000、Indirect Cost: ¥7,290,000)
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| Keywords | LSI / CMOS / SiP / low power / interface / wireless / inter-chin communication / inductive coupling |
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| Research Abstract |
The computation speed shows an exponential improvement due to the improvement over speed and integration of transistor by scaling on LSI fabrication process. On the other hand, conventional LSI system by printing board implementation, the transmission rate of inter-chip is limited because of the distance and restriction of the number of 10 channels. As a result the performance gap between transmission rate of inter-chip and computation speed became expanded. Nowadays, inter-chip communication becomes main key factor which determines performance of overall LSI system. 3-D stacked implementation in LSI system is a hot topic as a technique which is expected to solve the issue. Stacked inter-chip inductive communication which is proposed in the study is a inter-chip wireless communication technology where inductive coupling between inductors mounted in chip is used as input-output channels. Establishment of the technology becomes the key to realize high performance LSI system. In the study
… More
, Design theory for minimizing area of inductive coupling channels is established and the technique to reduce crosstalk between the channels, an issue occurs when channels are arranged, is proposed. By utilizing the technology, design, fabrication and evaluation of test chip with channels arranged in high-density are held and realization for high-speed inter-chip communication became the purpose of the study. Array channels with mounted proposed circuit technology are designed. Test chip is fabricated and the performance is evaluated. 4-phase Time Division Multiple Access (TDMA) is realized by creating 4-phase clock from phase-interpolation circuits. Crosstalk can be reduced by occupying Time Division Multiple Access and channel array pitch can be reduced to 30 μ m. As a result, 1mm^2 area of array is achieved. By arranging 1024 inductive coupling channel, communication performance (BER <10^<-13>) and wide bandwidth (1Tb/s) are improved. By changing modulation scheme into Bi-phase modulation scheme and improving receiver's noise-tolerance, 2mW of reduction in transmission power is achieved. Less
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