| Project/Area Number |
16300013
|
|---|
| Research Category |
Grant-in-Aid for Scientific Research (B)
|
| Allocation Type | Single-year Grants |
|---|
| Section | 一般 |
|---|
| Research Field |
Computer system/Network
|
|---|
| Research Institution | The University of Tokyo |
|---|
Principal Investigator |
SAKAI Shuichi The University of Tokyo, Graduate School of Information Science and Technology, Professor, 大学院情報理工学系研究科, 教授 (50291290)
|
|---|
| Co-Investigator(Kenkyū-buntansha) |
GOSHIMA Masahiro The University of Tokyo, Graduate School of Information Science and Technology, Associate Professor, 大学院情報理工学系研究科, 助教授 (90283639)
|
|---|
| Project Period (FY) |
2004 – 2006
|
| Project Status |
Completed (Fiscal Year 2006)
|
| Budget Amount *help |
¥14,800,000 (Direct Cost: ¥14,800,000)
Fiscal Year 2006: ¥1,900,000 (Direct Cost: ¥1,900,000)
Fiscal Year 2005: ¥5,900,000 (Direct Cost: ¥5,900,000)
Fiscal Year 2004: ¥7,000,000 (Direct Cost: ¥7,000,000)
|
|---|
| Keywords | microprocessor / low power / computer architecture / cycle level simulator / speculative execution / compiler / chip multiprocessor / thread / チップマルチプロセッサ |
|---|
| Research Abstract |
The followings are the research products for realizing next generation low power microprocessors.
First, we built up two types of cycle level simulators for the base of quantitative evaluations : the chip multiprocessor simulator and the clustered superscalar processor simulator. Next, we carried out two types of researches : (1) researches on system level low power technologies : and (2) researches on technologies for mitigating soft errors with reducing power consumption.
As system level low power technologies, we studied the followings.
1.1) the hot path detector exploiting branch predictors
1.2) improving program phase detection mechanisms based on signatures
1.3) dynamic estimation of thread level parallelism by OS support
1.4) power reduction by serializing on-chip buses
1.5) non-uniform shared cache on chip multiprocessors
As technologies for mitigating soft errors with reducing power consumptions, we studied the followings.
2.1) soft error mitigation exploiting horizontal and vertical parities
2.2) soft error mitigation on content addressable memories
2.3) measures against process anomalies and soft errors
We integrate the above technologies and showed the methodologies for reducing power and gaining efficiency on the next generation processors.
|
