Quantum-Inspired Reconfigurable Processor
| Project/Area Number |
16360167
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Electron device/Electronic equipment
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| Research Institution | The University of Tokyo |
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Principal Investigator |
FUJISHIMA Minoru The Univesity of Tokyo, Graduate School of Frontier Sciences, Professor, 大学院新領域創成科学研究科, 助教授 (60251352)
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| Project Period (FY) |
2004 – 2006
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| Project Status |
Completed (Fiscal Year 2006)
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| Budget Amount *help |
¥14,900,000 (Direct Cost: ¥14,900,000)
Fiscal Year 2006: ¥4,600,000 (Direct Cost: ¥4,600,000)
Fiscal Year 2005: ¥4,600,000 (Direct Cost: ¥4,600,000)
Fiscal Year 2004: ¥5,700,000 (Direct Cost: ¥5,700,000)
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| Keywords | parallel processor / quantum computer / quantum algorithm / emulator / FPGA / DIMD / FPGA / チップマルチプロセッサ / 量子コンピューティング / 逆問題 / 因数分解 / 並列処理 / 量子アルゴリズム / NP問題 |
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| Research Abstract |
A quantum computer is expected to solve the NP problem, such as factorization, at high speed, since it can verify all the solution candidates simultaneously. However, the final system of the quantum computer is still unclear. It is noted that not only hardware but also software with algorithm and benchmark tests is indispensable to realize practical operation. Hence, a quantum-computing emulator is necessary to inspect the algorithm. However, emulation of large-scale quantum algorithm is difficult, since quantum superposition is utilized in the quantum computer and 2^N memories are necessary to emulate N qubits. By replacing some qubits with classic bits and using quantum-macro operations, we have proposed a new quantum-computing emulator. In this emulator, by focusing on only a core calculation part, we have assigned classical bits for some calculation process and using unitary-macro operations for frequent quantum operations. As a result, we have succeeded to reduce memory usage. In implementation, we have fabricated a DIMD (dual-instruction multiple-data) processor with 192 parallel PE on FPGA with 40MHz clock and an operation converter which is a C-language software controlling processing and the unitary-macro operations. In this quantum-computing emulator, we have made an experiment on the factorization with a 64 bits integer by using Shor's algorithm, which is well-known algorithm for the quantum computer. Although this calculation is equivalent to computational complexity to use 320 qubit for on the quantum computer, as a result of experiment, 1,300 seconds are used for computation and only 40k-bit memory is required for this emulation
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Report
(4 results)
Research Products
(15 results)
