| Project/Area Number |
16560294
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Electron device/Electronic equipment
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| Research Institution | Japan Advanced Institute of Science and Technology |
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Principal Investigator |
KANEKO Mineo JAIST, School of Information Science, Professor, 情報科学研究科, 教授 (00185935)
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| Project Period (FY) |
2004 – 2005
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| Project Status |
Completed (Fiscal Year 2005)
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| Budget Amount *help |
¥3,500,000 (Direct Cost: ¥3,500,000)
Fiscal Year 2005: ¥1,900,000 (Direct Cost: ¥1,900,000)
Fiscal Year 2004: ¥1,600,000 (Direct Cost: ¥1,600,000)
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| Keywords | VLSI / Datapath synthesis / Clock signal / Asynchronous circuit / Control skew / EDA / Statistical delay analysis / ASIC / 非同期データパス / 遅延スキュー / 配線遅延 / アプリケーション特化専用LSI / 制御回路 |
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| Research Abstract |
In the current and future nanometer-technologies for VLSIs, clock distribution is chip-area consuming and power consuming, and also it makes the timing problem more serious. The clock-less data-path architecture, which excludes clock signal from the data-path part, would be one of the solutions for those problems relevant to clock distribution. The purpose of this research is to show the possibility and to develop design methodologies of the clock-less data-path. One clock-less data-path architecture considered in our study is the one which consists of a controller part driven by a clock signal and a data-path part driven by only control signals from the controller (a clock signal is not fed to the data-path part). The other is the one which consists of an asynchronous controller part and an asynchronous data-path part. The results obtained in this research are summarized as follows.
1.We have proposed the assignment constraint control signal scheduling considering both the data signal
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delay in the data-path part and control signal delay from the controller to each component in the data-path part. The scheduler has been incorporated into a new synthesis framework called "assignment-centric high-level synthesis" to form a complete synthesis system.
2.The difference of arrival timing of control signals is called "timing skew", and it has the potential to improve the speed of the data-path. We have formulated several skew optimization problems, studied there properties and developed optimization algorithms.
3.We have proposed an assignment-centric approach to the high-level synthesis for asynchronous data-paths. The major advantages of our method over conventional ones are (1) the efficiency in optimization and (2) statistical performance analysis.
4.To improve hardware utilization in the clock-less asynchronous data-path, a novel implementation of asynchronous register has been proposed. The synthesis system has been modified to meet a new register sharing model provided by the new register. We have verified the effectiveness of the new register through synthesis experiments. Less
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