| Budget Amount *help |
¥2,900,000 (Direct Cost: ¥2,900,000)
Fiscal Year 2005: ¥1,200,000 (Direct Cost: ¥1,200,000)
Fiscal Year 2004: ¥1,700,000 (Direct Cost: ¥1,700,000)
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| Research Abstract |
In the first year, the ways to reduce the phase noise of a frequency synthesizer is studies to extend the field applicable for the ring oscillators. The. obtained main results include the following two items. One is a design method of a loop filters for an integer-N PLL to achieve low phase noise characteristics in relation to the conventional method. The other is a proposal of a shaping approach of the phase noise of a fractional-N PLL.
By applying the proposed design method of the loop filter for an integer-N PLL, it becomes possible the set the bandwidth of the PLL because of an accurate modeling of the PLL. As the result, a loop filter the phase noise produced by the ring oscillator may be suppressed well can be designed.
With a fractional-N PLL, there is a problem how to calculate the changing divide number for each cycle. For this problem, a procedure to calculate a series of divide numbers using the genetic algorithm has been proposed.
In the second year, a prototype IC including proposed ring oscillators, a proposed phase comparator, a charge pump, a V/I converter and so on is designed and fabricated using VDEC service. Now an evaluation environment for the fabricated IC is being constructed.
Further, fundamental studies on the poly-phase filters realized by the switched capacitor technology, which may become applied to the receivers with the proposed ring oscillators, are performed. By using circuit simulation, it has been proved that the proposed approach is practical and a design scheme with low parameter sensitivities for a high order filter has been proposed. Real circuits are made to prove the effectiveness of the proposed filter and to evaluate its sensitivities in relation to the fluctuations of the element characteristics.
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