| Project/Area Number |
16H06679
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| Research Category |
Grant-in-Aid for Research Activity Start-up
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| Allocation Type | Single-year Grants |
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| Research Field |
High performance computing
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| Research Institution | The University of Tokyo |
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Principal Investigator |
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| Project Period (FY) |
2016-08-26 – 2018-03-31
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| Project Status |
Completed (Fiscal Year 2017)
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| Budget Amount *help |
¥2,990,000 (Direct Cost: ¥2,300,000、Indirect Cost: ¥690,000)
Fiscal Year 2017: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
Fiscal Year 2016: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000)
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| Keywords | メニーコアプロセッサ / GPU / SIMD / 境界要素法 / フレームワーク / 計算機システム / ソフトコンピューティング / OpenACC / 自動最適化 / Xeon Phi / ハイパフォーマンス・コンピューティング |
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| Outline of Final Research Achievements |
Nowadays, the number of computational environment using many-core processors is increasing. To bring out the efficient performance of many-core processors, it is important to efficiently use the Vector Processing Unit (VPU). However, the knowledge of hardware and compiler is required to efficiently use the VPU, and moreover, data structural changes are often required.
In this research, we propose a set of compiler directives for abstraction of data layout. We also implement a translator for the proposed directives. Furthermore, we propose a framework design to enhance the efficient vectorization. Also, we implement a BEM-BB framework using the proposed framework design.
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