| Budget Amount *help |
¥3,900,000 (Direct Cost: ¥3,000,000、Indirect Cost: ¥900,000)
Fiscal Year 2017: ¥1,950,000 (Direct Cost: ¥1,500,000、Indirect Cost: ¥450,000)
Fiscal Year 2016: ¥1,950,000 (Direct Cost: ¥1,500,000、Indirect Cost: ¥450,000)
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| Outline of Final Research Achievements |
We developed a multi-paradigm high-level hardware design framework that easily exploits on-chip memory blocks and memory bandwidth of an FPGA. The framework is based on Veriloggen, a Python-based domain-specific language for hardware design. The newly developed framework supports 3 different programming paradigms; The compiler supports Sequential, Stream, and RTL. In addition to the framework, we developed a highly-abstracted dataflow-based hardware compiler for deep neural networks.
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