Architecture and Design Method for High-Quality Hetero-Timing VLSI Systems
| Project/Area Number |
17300013
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Computer system/Network
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| Research Institution | The University of Tokyo |
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Principal Investigator |
NANYA Takashi The University of Tokyo, Research Center for Advanced Science and Technology, Professor, 先端科学技術研究センター, 教授 (80143684)
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| Co-Investigator(Kenkyū-buntansha) |
NAKAMURA Hiroshi The University of Tokyo, Research Center for Advanced Science and Technology, Associate Professor, 先端科学技術研究センター, 助教授 (20212102)
IMAI Masashi The University of Tokyo, Komaba Open Laboratory, Specially Appointed Associate Professor, 駒場オープンラボラトリー, 特任教員・特任助教授 (70323665)
KONDO Masaaki The University of Tokyo, Research Center for Advanced Science and Technology, Specially Appointed Associate Professor, 先端科学技術研究センター, 産学官連携研究員・特任助教授 (30376660)
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| Project Period (FY) |
2005 – 2006
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| Project Status |
Completed (Fiscal Year 2006)
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| Budget Amount *help |
¥15,000,000 (Direct Cost: ¥15,000,000)
Fiscal Year 2006: ¥5,700,000 (Direct Cost: ¥5,700,000)
Fiscal Year 2005: ¥9,300,000 (Direct Cost: ¥9,300,000)
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| Keywords | Hetero-Timing VLSI / Multi-Processor SoC / Task Scheduling / Low Power Consumption / Delay Variation / Asynchronous System / SDI Model / 1-out-of-4 Coding / ヘテロタイミング / VLSIシステム / 情報システム / ディペンダブルシステム |
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| Research Abstract |
In this research, we have shown that a pipeline scheduling method is effective to reduce energy consumption for applications which are iterative and have both latency and throughput constraints. Then, we have proposed a new scheduling method based on the simulated annealing for solving the energy optimization problem. We have shown some evaluation results of throughput, latency, and energy consumption for the traditional on-chip interconnect designs based on both a synchronous scheme and an asynchronous scheme. Then, we have proposed a new interconnect circuit which can work as both a synchronous repeater circuit and an asynchronous pipeline circuit. It can change dynamically in accordance with the requirement of processing applications.
We have proposed variation-aware delay cell libraries which consist of delay cells exhibiting a wide variety of delay variation characteristics considering the differences of the delay variations between PMOS transistors and NMOS transistors based on the Scalable-Delay-Insensitive model. The performance overhead can be reduced more than 30 percents compared to conventional bundled-data transfer circuits using these delay cell libraries. Then, we have focused on functional units in which a significant number of input bits may not change from the previous input in many cases. We have proposed a design method of asynchronous dual-rail circuits without redundant transitions in order to reduce energy consumption. We have also proposed a design method using the 1-out-of-4 encoding method to design low-power combinational circuits and latches. We have compared the proposed 1-out-of-4 encoded circuits with synchronous circuits in the future process technologies. It can be concluded that the 1-out-of-4 encoding method is an effective implementation to design high-performance low-power circuits in the future processes.
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Report
(3 results)
Research Products
(30 results)
