| Project/Area Number |
17300014
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Computer system/Network
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| Research Institution | Nagoya University |
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Principal Investigator |
TAKADA Hiroaki Nagoya University, Graduate School of Information Science, Professor, 大学院情報科学研究科, 教授 (60216661)
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| Co-Investigator(Kenkyū-buntansha) |
TOMIYAMA Hiroyuki Nagoya University, Graduate School of Information Science, Associate Professor, 大学院情報科学研究科, 助教授 (80362292)
YAMAMOTO Masaki Nagoya University, Graduate School of Information Science, Researcher, 大学院情報科学研究科, 研究員 (10402405)
HONDA Shinya Nagoya University, Graduate School of Information Science, Assistant Professor, 大学院情報科学研究科, 助手 (20402406)
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| Project Period (FY) |
2005 – 2006
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| Project Status |
Completed (Fiscal Year 2006)
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| Budget Amount *help |
¥7,000,000 (Direct Cost: ¥7,000,000)
Fiscal Year 2006: ¥3,000,000 (Direct Cost: ¥3,000,000)
Fiscal Year 2005: ¥4,000,000 (Direct Cost: ¥4,000,000)
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| Keywords | Cosimulation / Real-time OS / SystemC / Embedded systems / Multiprocessors / Shared memory |
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| Research Abstract |
In this research, we have developed technology and tools for fast cosimulation of embedded software and hardware. For the two years, we have completed the following achievements.
1. We have developed the two techniques for cosimulation of embedded multiprocessor systems.
(1) A flexible communication technique between multiple RTOS simulators and one or more hardware simulators.
(2) A technique for sending/receiving interrupts between RTOS simulators.
2. We have developed a synchronization technique between RTOS simulators and hardware simulators. A hardware simulator sends timer ticks to RTOS simulators, and a timer handler receives the ticks and updates an local timer in each RTOS simulator.
3. We have developed a technique for fast cosimulation on multi-core host computers. We have reduced the inter-simulator communication overhead speed by using not only RPC but also shared memory on a host computer.
4. We have developed a techniques for cosimulation with the SystemC language, which has become popular for hardware design and validation.
5. Based on the cosimulator which we have developed, we have also developed a methodology for efficient design and validation of embedded systems.
6. We have conducted a case study with a real-world application in order to evaluate the effectiveness of the HW/SW cosimulator developed in this research. An MPEG encoder/decoder application was used as a demonstrative example. On a multi-core host computer, two RTOS simulators, one HDL simulator and one C model were successfully and efficiently executed.
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