Development of Coarse-Grained Dynamic Self-Reconfigurable Device aiming for Reduction of Reconfiguration Overhead
| Project/Area Number |
17300016
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Computer system/Network
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| Research Institution | Ritsumeikan University (2007)
Kyoto University (2005-2006) |
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Principal Investigator |
NAKAMURA Yukihiro Ritsumeikan University, Research Organization of Science & Engineering, Professor (60283628)
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| Co-Investigator(Kenkyū-buntansha) |
OCHI Hiroyuki Kyoto University, Graduate School of Informatics, Associate Professor (40264957)
IZUMI Tomonori Ritsumeikan University, College of Science and Engineering, Associate Professor (30303887)
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| Project Period (FY) |
2005 – 2007
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| Project Status |
Completed (Fiscal Year 2007)
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| Budget Amount *help |
¥9,430,000 (Direct Cost: ¥8,800,000、Indirect Cost: ¥630,000)
Fiscal Year 2007: ¥2,730,000 (Direct Cost: ¥2,100,000、Indirect Cost: ¥630,000)
Fiscal Year 2006: ¥3,400,000 (Direct Cost: ¥3,400,000)
Fiscal Year 2005: ¥3,300,000 (Direct Cost: ¥3,300,000)
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| Keywords | reconfigurable architecture / dvnamic self-reconfiguration / plastic cell architecture / FPGA / coarse-grained reconfigurable device / セルアレイ型再構成アーキテクチャ / Plastic Cell Architecture / 性能及び回路面積の比較検討 / 高位合成 / レイアウト合成 / Plastc Cell Architecture |
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| Research Abstract |
In this project, we have studied on coarse-grained Plastic Cell Architecture (PCA), a dynamically self-reconfigurable massively-parallel processing machine based on wired-logic, in order to achieve drastic performance enhancement with practical applications by reducing reconfiguration overhead.
We have developed a simulation platform for dynamically self-reconfigurable architectures. Our platform enables us to make a quantitative analysis of relations between performance and the architecture parameters including operation granularity, reconfiguration granularity, data-bus bandwidth, reconfiguration bandwidth, and memory density. We have made some case studies using the platform. We have also developed an automated synthesis tool which covers various self-reconfigurable devices of different granularity parameters. Given a design in C language, our tool performs synthesis flow from operation resource allocation to placement and routing. We have also made some evaluations of architectures
… More
using our tool.
Based on the experiments so far, we have designed and fabricated a prototype chip of the proposed dynamically self-reconfigurable architecture. Although ALU-based coarse-grained reconfigurable devices are suitable for word-wise processing, we noticed that they are not efficiently used for sequential processing with complicated controls. Thus, we have developed an architecture which has dual ALU-array/RISC processor operating mode capability to achieve performance enhancement by changing operating mode of the device according to characteristics of target applications.
We should also notice that reconfigurable devices are more vulnerable to soft-errors than ASICs, because of large amount of SRAM for configuration. To overcome this disadvantage, we have studied on a dynamically reconfigurable architecture that diagnoses and repairs autonomously the soft-errors.
From our research in these three years described so far, we have acquired several key ideas and valuable knowledge on dynamically self-reconfigurable coarse-grained architectures, and clarified a prospect of showing their merits. Less
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Report
(4 results)
Research Products
(40 results)
