Processor Architecture with Program Protection Feature Using Cryptography
| Project/Area Number |
17500044
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Computer system/Network
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| Research Institution | Hiroshima City University |
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Principal Investigator |
KITAMURA Toshiaki Hiroshima City University, Faculty of Information Sciences, Professor, 情報科学部, 教授 (10324683)
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| Project Period (FY) |
2005 – 2006
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| Project Status |
Completed (Fiscal Year 2006)
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| Budget Amount *help |
¥3,200,000 (Direct Cost: ¥3,200,000)
Fiscal Year 2006: ¥1,500,000 (Direct Cost: ¥1,500,000)
Fiscal Year 2005: ¥1,700,000 (Direct Cost: ¥1,700,000)
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| Keywords | secure processor / public-key cryptography / processor architecture / copyright protection for programs |
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| Research Abstract |
1. Proposal of a secure processor
We have proposed a new type of secure processor which has these features:
1)encrypt only on program, not on data, 2)decryption key is selected based on virtual memory system not on process basis as usual, i.e. each page can be related to key in order to encrypt shared libraries;
2. Feasibility study on proposed secure processor
We evaluated DES and AES cryptosystem by designing by RTL level, and the point of hardware amount and decryption time, both systems are not so different. So, we employ AES, because of its superior security.
We designed a RTL model and software simulator of proposed secure processor based on ARM-like embedded processor to evaluate the increase of hardware and the degradation of performance. By this evaluation, we can conclude the demerits of this proposal are acceptable.
3. Penetration test for our secure processor
As our secure processor does not encrypt on data, we afraid the instructions are identified by observing the results of each instruction result with many input data. We assume three conditions: 1) adversary can use privileged function. 2) Adversary can probe memory bus and get memory access address and data by resolution of cache line size. 3)adversary can execute single target instruction using external interrupt or something; and we find the instruction can be identified one by one by several to several tens executions with deferent sets of register values. To protect program, we must consider some conditions will be restricted.
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Report
(3 results)
Research Products
(7 results)
