| Budget Amount *help |
¥3,500,000 (Direct Cost: ¥3,500,000)
Fiscal Year 2006: ¥1,700,000 (Direct Cost: ¥1,700,000)
Fiscal Year 2005: ¥1,800,000 (Direct Cost: ¥1,800,000)
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| Research Abstract |
1. Related technologies for this research such as moving picture encoding and decoding, high speed signal processing, low-power and low-leakages current for LSIs, etc have been investigated.
2. Various high speed motion vector estimation methods have been developed. To reduce power dissipation of video codec processors, a fast ME algorithm called a fast motion estimation algorithm employing adaptively assigned breaking-off condition search (AABCS) algorithm was developed. AABCS can improve processing speed of the conventional full-search (FS) method by a factor of more than 50, while maintaining visual quality of the FS method.
3. At clock frequency of 160 MHz and supply voltage of 1.0 V the power dissipation of a developed 90-nm CMOS video codec processor using AABCS and a gated-clock pulse scheme was reduced to 20 μW that was about 1/100 that of the same codec processor implementing a conventional FS method.
4. In order to reduce both leakage current and dynamic power, a self-controllable voltage level (SVL) circuit, which can supply a maximum DC voltage to an active-load circuit on request or can decrease the DC voltage supplied to a load circuit in stand-by mode, was developed. This SVL circuit can drastically reduce stand-by leakage power of CMOS logic circuits and SRAMs with minimal overheads in terms of chip area and speed. The stand-by power of 2-Kb SRAM incorporating the SVL circuit was 1.4 mW that was about 4.9% of that of an equivalent conventional 2-Kbit SRAM. The active power of this new SRAM was 620 mW, 28.8% of that of the equivalent conventional 2-Kbit SRAM. The read-access time of this new SRAM was 553 psec, that is, only 2.6% longer than that of the equivalent conventional 1-Kb SRAM.
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