| Budget Amount *help |
¥4,680,000 (Direct Cost: ¥3,600,000、Indirect Cost: ¥1,080,000)
Fiscal Year 2020: ¥1,040,000 (Direct Cost: ¥800,000、Indirect Cost: ¥240,000)
Fiscal Year 2019: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000)
Fiscal Year 2018: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000)
Fiscal Year 2017: ¥1,040,000 (Direct Cost: ¥800,000、Indirect Cost: ¥240,000)
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| Outline of Final Research Achievements |
To improve thermal fatigue resistance of the joint of the power semiconductor chip, the dispersion method of pillar-shaped intermetallic compounds (IMCs) generated in lead-free solder was investigated. For Sn-Ag-Cu-In system solder, the bonding temperature and the cooling rate from it to be required for formation of pillar-shaped IMCs were clarified. The power cycle test that simulates rapid heating and cooling cycles loaded to the power semiconductor chip was conducted and it was found that the joint with dispersed pillar-shaped IMCs has an excellent suppressing effect on fatigue crack propagation. Moreover, a Sn-Sb-Ag system alloy with small amount of Ni and Ge was developed as a new high-temperature lead-free solder to improve the thermal fatigue resistance of solder itself.
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