Research of the reconfigurable processor for large-scale numerical computation
| Project/Area Number |
18300016
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Computer system/Network
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| Research Institution | Hiroshima City University |
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Principal Investigator |
HIRONAKA Tetsuo Hiroshima City University, 情報科学研究科, 教授 (10253486)
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| Co-Investigator(Kenkyū-buntansha) |
谷川 一哉 広島市立大学, 情報科学研究科, 助教 (80382373)
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| Co-Investigator(Renkei-kenkyūsha) |
TANIGAWA Kazuya 広島市立大学, 情報科学研究科, 助教 (80382373)
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| Project Period (FY) |
2006 – 2009
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| Project Status |
Completed (Fiscal Year 2009)
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| Budget Amount *help |
¥15,770,000 (Direct Cost: ¥12,800,000、Indirect Cost: ¥2,970,000)
Fiscal Year 2009: ¥5,720,000 (Direct Cost: ¥4,400,000、Indirect Cost: ¥1,320,000)
Fiscal Year 2008: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
Fiscal Year 2007: ¥5,720,000 (Direct Cost: ¥4,400,000、Indirect Cost: ¥1,320,000)
Fiscal Year 2006: ¥2,900,000 (Direct Cost: ¥2,900,000)
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| Keywords | リコンフィギャラブルプロセッサ / 高精度数値計算 / リコンフィギャラブル / 多倍長浮動小数点演算 / ディジットシリアル浮動小数点演算器 / 大規模数値計算 / 8倍精度浮動小数点演算器 / チップ面積 / I / Oピン / 単位面積当たりの性能 / 計算機アーキテクチャ / 高精度整数演算器 / 高精度浮動小数点演算器 / 演算器間ネットワーク / デジットシリアル演算器 / コンパイラ / メモリボトルネック |
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| Research Abstract |
Scientific calculations such as Loop integrals and CG methods require multiple-precision floating-point operations. In this project, to achieve faster multiple-precision floating-point operations used in these applications, we propose HP-DSFP architecture. In HP-DSFP architecture, by using the digit-serial computation scheme, we achieved 2.4 times higher performance compared with the conventional arithmetic unit using the same chip area.
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Report
(6 results)
Research Products
(37 results)
