Designing of Ultra High-Speed and Compact Variable Latency PipelinedArithmetic Units
Project/Area Number |
19700037
|
Research Category |
Grant-in-Aid for Young Scientists (B)
|
Allocation Type | Single-year Grants |
Research Field |
Computer system/Network
|
Research Institution | Tohoku University |
Principal Investigator |
EGAWA Ryusuke Tohoku University, サイバーサイエンスセンター, 助教 (80374990)
|
Project Period (FY) |
2007 – 2009
|
Project Status |
Completed (Fiscal Year 2009)
|
Budget Amount *help |
¥3,650,000 (Direct Cost: ¥3,200,000、Indirect Cost: ¥450,000)
Fiscal Year 2009: ¥780,000 (Direct Cost: ¥600,000、Indirect Cost: ¥180,000)
Fiscal Year 2008: ¥1,170,000 (Direct Cost: ¥900,000、Indirect Cost: ¥270,000)
Fiscal Year 2007: ¥1,700,000 (Direct Cost: ¥1,700,000)
|
Keywords | ウェーブパイプライン / VLSI / 回路設計 / 熱解析 / 等遅延回路 / 低消費電力 / 可変レイテン / 算術演算 / 可変レイテンシ |
Research Abstract |
To realize low-power and high-speed arithmetic units with future CMOS technologies, this project focused on and carried out research that concerned with a circuit compaction technique and a delay balancing technique. An input bit-sliced circuit partitioning method for circuit scale compaction and a delay balancing methods based on logical effort theory for wave pipelines have been proposed and evaluated. The experimental results clarified the effective of both proposals.
|
Report
(4 results)
Research Products
(12 results)