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Development of transistors with negative-CTE gate electrode for introducing strained Si

Research Project

Project/Area Number 19K21953
Research Category

Grant-in-Aid for Challenging Research (Exploratory)

Allocation TypeMulti-year Fund
Review Section Medium-sized Section 21:Electrical and electronic engineering and related fields
Research InstitutionTohoku University

Principal Investigator

Kino Hisashi  東北大学, 学際科学フロンティア研究所, 助教 (10633406)

Project Period (FY) 2019-06-28 – 2021-03-31
Project Status Completed (Fiscal Year 2020)
Budget Amount *help
¥5,980,000 (Direct Cost: ¥4,600,000、Indirect Cost: ¥1,380,000)
Fiscal Year 2020: ¥2,860,000 (Direct Cost: ¥2,200,000、Indirect Cost: ¥660,000)
Fiscal Year 2019: ¥3,120,000 (Direct Cost: ¥2,400,000、Indirect Cost: ¥720,000)
Keywords負熱膨張 / トランジスタ / 半導体 / 負の熱膨張 / 結晶歪み / 移動度
Outline of Research at the Start

高度情報化社会を支える半導体集積回路を構成するトランジスタの高性能化方法の一つとして、ひずみシリコン技術が挙げられる。近年、シリコンに導入されるひずみ量が飽和しつつあり、新しいひずみ導入技術が強く求められている。本研究ではトランジスタのゲート電極に負の熱膨張係数を有する材料を適用し、冷却膨張などの特徴を応用することでシリコンへのひずみ導入を試みる。本研究構造はトランジスタのチャネル領域への直接的作用による大きなひずみ導入を可能としながら、従来の薄膜堆積と同等のひずみ導入方法であるため、様々な基板に適用可能な非常に汎用性の高い意義のある技術である。

Outline of Final Research Achievements

Large-scale integrated circuits, which support the current advanced information society from the hardware side, are mainly composed of transistors. The performances have been improved by scaling down transistors. In addition, in recent years, high performance has been achieved by the combined use of strained-silicon technology. However, the amount of strain introduced is becoming saturated, and a new strain introduction technique is strongly required.
This study creates an entirely new strain introduction technique using materials with negative thermal expansion coefficients.
Focusing on manganese nitride as a material with a negative thermal expansion coefficient, we established a process technology for transistors with manganese nitride. The mobility improvement was obtained in the fabricated transistor.

Academic Significance and Societal Importance of the Research Achievements

高度情報化社会を支える半導体集積回路の性能向上のためにはシリコンへのひずみ導入技術はもはやなくてはならない技術の一つである。一方、ひずみシリコン技術が実用化されてから大よそ15年が経過したが、現状のひずみ導入法では印加可能なひずみ量が飽和しつつあり、さらなるひずみを導入可能な技術が早急に求められている。このような背景下において、本研究は高度情報化社会をさらに発展させ得る社会的意義を有しており、トランジスタを構成する要素に負の熱膨張係数を有する材料を導入する本研究は学術的にも高い意義を有する。

Report

(3 results)
  • 2020 Annual Research Report   Final Research Report ( PDF )
  • 2019 Research-status Report
  • Research Products

    (3 results)

All 2020

All Journal Article (2 results) (of which Peer Reviewed: 2 results,  Open Access: 1 results) Presentation (1 results) (of which Int'l Joint Research: 1 results)

  • [Journal Article] Generation of STDP With Non-Volatile Tunnel-FET Memory for Large-Scale and Low-Power Spiking Neural Networks2020

    • Author(s)
      Kino Hisashi、Fukushima Takafumi、Tanaka Tetsu
    • Journal Title

      IEEE Journal of the Electron Devices Society

      Volume: 8 Pages: 1266-1271

    • DOI

      10.1109/jeds.2020.3025336

    • Related Report
      2020 Annual Research Report
    • Peer Reviewed / Open Access
  • [Journal Article] Symmetric and asymmetric spike-timing-dependent plasticity function realized in a tunnel-field-effect-transistor-based charge-trapping memory2020

    • Author(s)
      Kino Hisashi、Fukusima Takafumi、Tanaka Tetsu
    • Journal Title

      Japanese Journal of Applied Physics

      Volume: 59 Issue: SG Pages: SGGB12-SGGB12

    • DOI

      10.35848/1347-4065/ab6867

    • Related Report
      2020 Annual Research Report
    • Peer Reviewed
  • [Presentation] Development of Non-Volatile Tunnel-FET Memory as a Synaptic Device for Low-Power Spiking Neural Networks2020

    • Author(s)
      Hisashi Kino
    • Organizer
      2020 4th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)
    • Related Report
      2020 Annual Research Report
    • Int'l Joint Research

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Published: 2019-07-04   Modified: 2022-01-27  

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