| Project/Area Number |
19K24336
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| Research Category |
Grant-in-Aid for Research Activity Start-up
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| Allocation Type | Multi-year Fund |
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| Review Section |
1001:Information science, computer engineering, and related fields
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| Research Institution | Tohoku University |
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Principal Investigator |
YLIMAEYRY VILLE 東北大学, 電気通信研究所, 助教(研究特任) (80846519)
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| Project Period (FY) |
2019-08-30 – 2021-03-31
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| Project Status |
Granted (Fiscal Year 2019)
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| Budget Amount *help |
¥2,860,000 (Direct Cost: ¥2,200,000、Indirect Cost: ¥660,000)
Fiscal Year 2020: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
Fiscal Year 2019: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
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| Keywords | post-quantum / cryptography / hardware implementation / side-channel analysis / hardware / side-channel attacks |
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| Outline of Research at the Start |
We study efficient and secure hardware implementation of Post-Quantum Cryptography algorithms. Further, we evaluate the security of the implemented hardware accelerators. This evaluation is done to ensure that the implemented algorithms are secure against so called side-channel attacks, that exploit the physical properties of the device the algorithm is implemented on.
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| Outline of Annual Research Achievements |
We began by choosing for our researched algorithm the SABER post-quantum cryptographic (PQC) key exchange algorithm, which is a candidate in the National Institute of Standards and Technology (NIST) competition for the next family of cryptographic algorithms for key exchange electronic communication. SABER is especially suited for efficient hardware implementation because of its simpler multiplication algorithm compared to the other competition candidates. This makes research of its hardware implementation quite impactful. The NIST competition for PQC algorithms has now progressed to it's second phase where the hardware implementations of the algorithms are evaluated, which makes this research very topical.
We planned the hardware design of the algorithm based on its software reference, and mapped hardware design space of the implementation of the largest modules, namely the hashing functions of SHA function family (namely SHA-256 and SHAKE-128), and the polynomial multiplication modules, which take the most area in digital logic and also processing time in the cryptographic operations.
Next, we will compare our design with the reference given by the algorithm authors, evaluate the cost-performance tradeoffs between the designs. Further, we will consider attacks that use information about the device such as power consumption or electro-magnetic radiation leaking from the device (side-channel information), for example, pinpoint the possible attackable modules, and propose countermeasures against such attacks.
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| Current Status of Research Progress |
Current Status of Research Progress
3: Progress in research has been slightly delayed.
Reason
Developments in the field have caused us to revise our design to meet the cutting edge of the implementation methods. We will update the design to include optimization techniques from ongoing research projects by other research groups.
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| Strategy for Future Research Activity |
We will continue with our original research plan of implementing a post-quantum cryptographic circuit in hardware with side-channel attack countermeasures. Our challenge will be to improve the hardware cost to processing throughput efficiency of the design compared to the original authors' design. We will pursue a massively parallelizable design style for our polynomial multiplication that allows for faster processing, and has not been proposed in other works this far.
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