Study on Vector Architecture for both Programmability and Peak Performance
| Project/Area Number |
20300015
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Computer system/Network
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| Research Institution | The University of Tokyo |
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Principal Investigator |
GOSHIMA Masahiro The University of Tokyo, 大学院・情報理工学系研究科, 准教授 (90283639)
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| Co-Investigator(Kenkyū-buntansha) |
SAKAI Syuichi 東京大学, 情報理工学系研究科, 教授 (50291290)
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| Project Period (FY) |
2008 – 2011
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| Project Status |
Completed (Fiscal Year 2010)
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| Budget Amount *help |
¥18,200,000 (Direct Cost: ¥14,000,000、Indirect Cost: ¥4,200,000)
Fiscal Year 2010: ¥8,450,000 (Direct Cost: ¥6,500,000、Indirect Cost: ¥1,950,000)
Fiscal Year 2009: ¥7,150,000 (Direct Cost: ¥5,500,000、Indirect Cost: ¥1,650,000)
Fiscal Year 2008: ¥2,600,000 (Direct Cost: ¥2,000,000、Indirect Cost: ¥600,000)
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| Keywords | 計算機アーキテクチャ / ベクトル処理 / SIMD / スーパスカラ・プロセッサ / マルチスレッド・プロセッサ / レジスタ・ファイル / レジスタ・キャッシュ / 計算機システム / コンピュータアーキテクチャ / スーパスカラプロセッサ / レジスタキャッシュ |
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| Research Abstract |
Although SIMD plays an important role in vector processing, suffers from low programmability and cannot cope with new applications which are becoming more complicated. This research places equal emphasis on programmability and for peak performance. Switchon-Future-Event multithreading achieves maximum of 33.5% performance improvement without sacrificing programmability. Increase in are of the register file cause by the multithreading is relaxed by the Non-latency-Oriented Register Cache System. Simulation results show the area is reduced to 24.9%.
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Report
(4 results)
Research Products
(53 results)
