Investigation of True Scalable CMOS Integrated Circuit
| Project/Area Number |
21246056
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| Research Category |
Grant-in-Aid for Scientific Research (A)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Electron device/Electronic equipment
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| Research Institution | Tokyo Institute of Technology |
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Principal Investigator |
MASU Kazuya 東京工業大学, ソリューション研究機構, 教授 (20157192)
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| Project Period (FY) |
2009 – 2012
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| Project Status |
Completed (Fiscal Year 2012)
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| Budget Amount *help |
¥30,940,000 (Direct Cost: ¥23,800,000、Indirect Cost: ¥7,140,000)
Fiscal Year 2012: ¥11,180,000 (Direct Cost: ¥8,600,000、Indirect Cost: ¥2,580,000)
Fiscal Year 2011: ¥9,490,000 (Direct Cost: ¥7,300,000、Indirect Cost: ¥2,190,000)
Fiscal Year 2010: ¥10,270,000 (Direct Cost: ¥7,900,000、Indirect Cost: ¥2,370,000)
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| Keywords | 電子デバイス / 集積回路 / スケーリング / CMOS / シリコン / ナノ配線 / シグナルインテグリティ / インテグリティ / 揺らぎ / ばらつき |
|---|
| Research Abstract |
Scaling of Si CMOS has been brought the performance improvement and low cost at the same time for long time. It is recognized that low cost is originated from the reduction of chip area, i.e., circuit area. When the high performance circuit is designed using the advanced CMOS process, if the chip area is not reduced, the design is not meaningful in the economical viewpoint． In this project, we have engaged in the design of digital and RF CMOS circuit, which has the scalability, i.e., the circuit which is designed using the advance CMOS process has the higher performance and the circuit area reduction at the same time. These results has been supported by the CMOS circuit design, fabrication and evaluation using 180nm, 90nm, 65nm and 40nm CMOS.
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Report
(5 results)
Research Products
(123 results)
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[Presentation] Path Clustering for Adaptive Test2010
Author(s)
Takumi Uezono, Tomoyuki Takahashi, Michihiro Shintani, Kazumi Hatayama, Kazuya Masu, Hiroyuki Ochi, Takashi Sato
Organizer
IEEE VLSI Test Symposium
Place of Presentation
California, USA
Year and Date
2010-04-19
Related Report
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[Presentation] pHセンサ用ISFET特性のモデリング2009
Author(s)
藤原琢, 石原昇, 天川修平, 田追裕貴, 野村聡, 小西敏文, 町田克之, 益一哉
Organizer
2009年(平成21年)秋季第70回応用物理学会学術講演会
Place of Presentation
富山,日本
Year and Date
2009-09-08
Related Report
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