On Establishment of General Synchronous Circuit Design Methodology to Enhance Delay Variation Robustness
| Project/Area Number |
21300012
|
|---|
| Research Category |
Grant-in-Aid for Scientific Research (B)
|
| Allocation Type | Single-year Grants |
|---|
| Section | 一般 |
|---|
| Research Field |
Computer system/Network
|
|---|
| Research Institution | Tokyo Institute of Technology (2012)
Osaka University (2009-2011) |
|---|
Principal Investigator |
TAKAHASHI Atsushi 東京工業大学, 大学院・理工学研究科, 准教授 (30236260)
|
|---|
| Project Period (FY) |
2009 – 2012
|
| Project Status |
Completed (Fiscal Year 2012)
|
| Budget Amount *help |
¥10,400,000 (Direct Cost: ¥8,000,000、Indirect Cost: ¥2,400,000)
Fiscal Year 2012: ¥2,210,000 (Direct Cost: ¥1,700,000、Indirect Cost: ¥510,000)
Fiscal Year 2011: ¥2,470,000 (Direct Cost: ¥1,900,000、Indirect Cost: ¥570,000)
Fiscal Year 2010: ¥2,210,000 (Direct Cost: ¥1,700,000、Indirect Cost: ¥510,000)
Fiscal Year 2009: ¥3,510,000 (Direct Cost: ¥2,700,000、Indirect Cost: ¥810,000)
|
|---|
| Keywords | VLSI設計技術 / 同期回路 / 耐遅延変動特性 / 遅延エラー検出回復方式 / 可変 レイテンシ回路 / 可変レイテンシ回路 / 実効クロック周期 / 一般同期方式 / クロック / エラー検出回復方式 / 桁上げ伝搬加算器 / 遅延分布 / 故障検出回復方式 / 動的遅延解析 |
|---|
| Research Abstract |
In order to establish new design methodology that enable us to design and manufacture high-performance and high-reliable integrated circuits, a fast delay distribution estimation method that has enough accuracy was developed. Also, performance and performance improvement ratio of variable latency circuits in which delay error detection/correction mechanism is used were evaluated for various circuit, and a guideline to synthesize high-performance and high-reliable integrated circuits efficiently was obtained.
|
Report
(5 results)
Research Products
(41 results)
