Study on calibration technique of large scale mixed-signal integrated circuits

• Project/Area Number: 21760264
• Research Category: Grant-in-Aid for Young Scientists (B)
• Allocation Type: Single-year Grants
• Research Field: Electron device/Electronic equipment
• Research Institution: Keio University
• Principal Investigator: ISHIKURO Hiroki Keio University, 理工学部, 准教授 (80433738)
• Project Period (FY): 2009 – 2010
• Project Status: Completed (Fiscal Year 2010)
• Budget Amount: ¥4,550,000 (Direct Cost: ¥3,500,000、Indirect Cost: ¥1,050,000); Fiscal Year 2010: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000); Fiscal Year 2009: ¥3,250,000 (Direct Cost: ¥2,500,000、Indirect Cost: ¥750,000)
• Keywords: アナログディジタル混載回路 / モニター回路 / キャリブレーション / サンプリング回路

Research Abstract

A monitoring circuit which can detect frequency and transient response of analog circuit blocks in large scale mixed-signal integrated circuits has been developed. A sampling circuit with both positive and negative bootstrapped clock generator has been proposed. Fabricated test chips successfully demonstrated the wide frequency and dynamic range operation. An area efficient phase interpolator has been proposed and designed for the monitoring of phase characteristics of the analog circuit blocks. The size of the developed monitoring circuit is smaller than 0.1mm-square and can be embedded in the LSI for the monitoring and calibration of analog circuit blocks.

Research Products

• [Journal Article] A Power Scalable SAR-ADC in 0.18um-CMOS with 0.5V Nano-Watt Operation (2011)
  • Author(s): Ryota Sekimoto, Akira Shikata, Hiroki Ishikuro
  • Journal Title: Proc.1st International Symposium on Access Spaces in press.
  • Peer Reviewed
• [Journal Article] A 90nm CMOS Highly Linear Clock Bootstrapped RF Sampler Operating at Wide Frequency Range of 0.5GHz to 5GHz (2009)
  • Author(s): M.Sato, H.Abe, M.Hamada, H.Majima, T.Kuroda, H.Ishikuro
  • Journal Title: in Proc.2009 IEEE Radio Frequency Integrated Circuits Symposium Pages: 391-394
  • Peer Reviewed
• [Presentation] A Power Scalable SAR-ADC in 0.18um-CMOS with 0.5V Nano-Watt Operation (2011)
  • Author(s): Ryota Sekimoto, Akira Shikata, Hiroki Ishikuro
  • Organizer: to be presented at 1st International Symposium on Access Spaces
  • Place of Presentation: Yokohama, Japan.
  • Year and Date: 2011-06-18
• [Presentation] 0.5V動作6-bitスケーラブル位相補間器 (2010)
  • Author(s): 熊木聡
  • Organizer: 電子情報通信学会集積回路研究会
  • Place of Presentation: 東京
  • Year and Date: 2010-12-16
• [Presentation] アナログ離散時間信号処理のための高線形かつ広帯域サンプリング回路 (2009)
  • Author(s): 佐藤守、阿部寛之、黒田忠広、石黒仁揮
  • Organizer: 電子情報通信学会集積回路研究会、電子情報通信学会技術研究報告 Vol.109, No214,pp.147-152
  • Place of Presentation: 東京
  • Year and Date: 2009-10-02
• [Presentation] A 90nm CMOS Highly Linear Clock Bootstrapped RF Sampler Operating at Wide Frequency Range of 0.5GHz to 5GHz (2009)
  • Author(s): M.Sato, H.Abe, M.Hamada, H.Majima, T.Kuroda, H.Ishikuro
  • Organizer: 2009 IEEE Radio Frequency Integrated Circuits Symposium
  • Place of Presentation: Boston, MA, USA.
  • Year and Date: 2009-06-09
• [Remarks] ホームページ等
  • URL: http://www.iskr.elec.keio.ac.jp