| Budget Amount *help |
¥18,200,000 (Direct Cost: ¥14,000,000、Indirect Cost: ¥4,200,000)
Fiscal Year 2013: ¥3,120,000 (Direct Cost: ¥2,400,000、Indirect Cost: ¥720,000)
Fiscal Year 2012: ¥6,240,000 (Direct Cost: ¥4,800,000、Indirect Cost: ¥1,440,000)
Fiscal Year 2011: ¥5,330,000 (Direct Cost: ¥4,100,000、Indirect Cost: ¥1,230,000)
Fiscal Year 2010: ¥3,510,000 (Direct Cost: ¥2,700,000、Indirect Cost: ¥810,000)
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| Research Abstract |
The aim of this research is to develop a new paradigm VLSI design methodology which relaxes design margin and realizes high-performance VLSI with high-dependability. In this research, we developed a MOS/magnetic-tunnel-junction-hybrid logic-circuit style for realizing a PVT-variation-aware VLSI processor with higher performance capability. For applying the proposed method to large-scale circuit structures, an optimization algorithm of circuit parameters based on evolutionary computation technique was also examined.
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