| Budget Amount *help |
¥19,500,000 (Direct Cost: ¥15,000,000、Indirect Cost: ¥4,500,000)
Fiscal Year 2012: ¥6,500,000 (Direct Cost: ¥5,000,000、Indirect Cost: ¥1,500,000)
Fiscal Year 2011: ¥6,500,000 (Direct Cost: ¥5,000,000、Indirect Cost: ¥1,500,000)
Fiscal Year 2010: ¥6,500,000 (Direct Cost: ¥5,000,000、Indirect Cost: ¥1,500,000)
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| Research Abstract |
In this work, a fundamental theory of scalable RF transceiver has been studies for realizing 1Tbps ultra-high-speed wireless communication. The key technology for the scalable RF transceiver is the improvement of gain, linearity and noise characteristics, and a circuit technique to maintain the circuit performance even with the process fluctuation. In this work, the proposed digital RF technique is applied to realize a self-calibration of the60GHz wireless transceiver implemented by 65nm CMOS. The phase noise degradation is avoided by using the proposed injection-locked oscillator, which results in a 20-dB improvement in the phase noise. Finally, a 20Gbps wireless transceiver has been realized, which is the fastest among wireless transceiver ICs.
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